- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378737 > UPD44321362GF-A50 (NEC Corp.) 32M-BIT ZEROSB SRAM PIPELINED OPERATIO PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD44321362GF-A50 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-BIT ZEROSB SRAM PIPELINED OPERATIO |
| 中文描述： | 32兆位ZEROSB SRAM的流水線OPERATIO |
| 文件頁(yè)數(shù)： | 15/24頁(yè) |
| 文件大?。?/td> | 299K |
| 代理商： | UPD44321362GF-A50 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)
15
Data Sheet M16024EJ5V0DS
μ
PD44321182, 44321362
Read and Write Cycle
Parameter
Symbol
-A50 (200 MHz)
Unit
Notes
Standard
Alias
MIN.
MAX.
Cycle time
TKHKH
TCYC
5
–
ns
Clock access time
TKHQV
TCD
–
3.2
ns
Output enable access time
TGLQV
TOE
–
3.2
ns
Clock high to output active
TKHQX1
TDC1
1.5
–
ns
1, 2
Clock high to output change
TKHQX2
TDC2
1.5
–
ns
Output enable to output active
TGLQX
TOLZ
0
–
ns
1
Output disable to output High-Z
TGHQZ
TOHZ
0
3.2
ns
1
Clock high to output High-Z
TKHQZ
TCZ
1.5
3.2
ns
1, 2
Clock high pulse width
TKHKL
TCH
1.8
–
ns
Clock low pulse width
TKLKH
TCL
1.8
–
ns
Setup times
Address
TAVKH
TAS
1.5
–
ns
Address advance
TADVVKH
TADVS
Clock enable
TEVKH
TCES
Chip enable
TCVKH
TCSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Hold times
Address
TKHAX
TAH
0.5
–
ns
3
Address advance
TKHADVX
TADVH
(1.0)
(–)
Clock enable
TKHEX
TCEH
Chip enable
TKHCX
TCSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Power down entry time
TZZE
TZZE
–
10
ns
Power down recovery time
TZZR
TZZR
–
10
ns
Notes 1.
Transition is measured
±
200 mV from steady state.
2.
To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than
TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus
contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (T
A
min.,
V
DD
max.) than TKHQZ, which is a max. parameter (worse case at T
A
max., V
DD
min.).
3.
These values apply when V
DD
= 3.3 V
±
0.165 V with a 3.3 V LVTTL interface, or when V
DD
= 2.5 V
±
0.125 V with a 2.5 V LVTTL interface.
Values in parentheses apply when V
DD
= 3.3 V
±
0.165 V with a 2.5 V LVTTL interface.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD444001LE-10 | 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT |
| UPD444001 | 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT |
| UPD444001LE-11 | 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT |
| UPD444001LE-12 | 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT |
| UPD444012AGY-B10X-MJH | 4M-BIT CMOS STATIC RAM 256K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44324182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W |
| UPD44324185BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324365BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。