參數(shù)資料
型號： UPD44321182
廠商： NEC Corp.
英文描述： 32M-BIT ZEROSB SRAM PIPELINED OPERATIO
中文描述： 32兆位ZEROSB SRAM的流水線OPERATIO
文件頁數(shù)： 8/24頁
文件大小： 299K
代理商： UPD44321182
8
Data Sheet M16024EJ5V0DS
μ
PD44321182, 44321362
[
μ
PD44321362]
A0 to A19
MODE
CLK
/CKE
ADV
/BW1
/BW2
/BW3
/BW4
/WE
/G
/CE
CE2
/CE2
Address
register 0
Burst
logic
Write address
register 0
Write registry and
data coherency
control logic
Write
drivers
D
ADV
K
A1
A1’
S
Read
logic
Input
O
E
I/O1 to I/O32
I/OP1 to I/OP4
20
18
20
20
20
36
36
36
36
Write address
register 1
O
E
Input
36
ZZ
Power down control
K
Memory Cell Array
1,024 x 36 columns
(37,748,736 bits)
1,024 rows
Burst Sequence
[
μ
PD44321362]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A19 to A2, A1, A0
1st Burst Address
A19 to A2, A1, /A0
2nd Burst Address
A19 to A2, /A1, A0
3rd Burst Address
A19 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 0
A19 to A2, 1, 1
1st Burst Address
A19 to A2, 0, 1
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 0
2nd Burst Address
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 0, 1
3rd Burst Address
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 0
相關(guān)PDF資料
PDF描述
UPD44321362GF-A50 32M-BIT ZEROSB SRAM PIPELINED OPERATIO
UPD444001LE-10 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT
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