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參數(shù)資料
| 型號： | UPD44321182 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-BIT ZEROSB SRAM PIPELINED OPERATIO |
| 中文描述： | 32兆位ZEROSB SRAM的流水線OPERATIO |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 299K |
| 代理商： | UPD44321182 |
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MOS INTEGRATED CIRCUIT
μ
PD44321182, 44321362
32M-BIT ZEROSB
TM
SRAM
PIPELINED OPERATION
Document No. M16024EJ5V0DS00 (5th edition)
Date Published April 2005 NS CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2002, 2005
Description
The
μ
PD44321182 is a 2,097,152-word by 18-bit and the
μ
PD44321362 is a 1,048,576-word by 36-bit ZEROSB
static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44321182 and
μ
PD44321362 are optimized to eliminate dead cycles for read to write, or write to read
transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and
output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input
(CLK).
The
μ
PD44321182 and
μ
PD44321362 are suitable for applications which require synchronous operation, high speed,
low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The
μ
PD44321182 and
μ
PD44321362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for
high density and low capacitive loading.
Features
Low voltage core supply : V
DD
= 3.3 ± 0.165 V / 2.5 ± 0.125 V
Synchronous operation
100 percent bus utilization
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for pipelined operation
All registers triggered off positive clock edge
3.3V or 2.5V LVTTL Compatible : All inputs and outputs
Fast clock access time : 3.2 ns (200 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4 (
μ
PD44321362)
/BW1 and /BW2 (
μ
PD44321182)
Three chip enables for easy depth expansion
Common I/O using three state outputs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44321182GF-A50(A) | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD44324182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W |
| UPD44324185BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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