參數(shù)資料
型號(hào)： UPD44321182
廠商： NEC Corp.
英文描述： 32M-BIT ZEROSB SRAM PIPELINED OPERATIO
中文描述： 32兆位ZEROSB SRAM的流水線OPERATIO
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 299K
代理商： UPD44321182
7
Data Sheet M16024EJ5V0DS
μ
PD44321182, 44321362
Block Diagrams
[
μ
PD44321182]
A0 to A20
MODE
CLK
/CKE
ADV
/BW1
/BW2
/WE
/G
/CE
CE2
/CE2
Address
register 0
Burst
logic
Write address
register 0
Write registry and
data coherency
control logic
Write
drivers
D
ADV
K
A1
A1’
S
Read
logic
Input
O
E
I/O1 to I/O16
I/OP1, I/OP2
21
19
21
21
21
18
18
18
18
Write address
register 1
O
E
Input
18
ZZ
Power down control
K
Memory Cell Array
2,048 x 18 columns
(37,748,736 bits)
1,024 rows
Burst Sequence
[
μ
PD44321182]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A20 to A2, A1, A0
1st Burst Address
A20 to A2, A1, /A0
2nd Burst Address
A20 to A2, /A1, A0
3rd Burst Address
A20 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 0
A20 to A2, 1, 1
1st Burst Address
A20 to A2, 0, 1
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 0
2nd Burst Address
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 0, 1
3rd Burst Address
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 0
相關(guān)PDF資料
PDF描述
UPD44321362GF-A50 32M-BIT ZEROSB SRAM PIPELINED OPERATIO
UPD444001LE-10 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT
UPD444001 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT
UPD444001LE-11 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT
UPD444001LE-12 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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