參數(shù)資料
型號: UPD31172F1-48-FN
廠商: NEC Corp.
英文描述: VRC4172TM COMPANION CHIP FOR VR4121TM
中文描述: VRC4172TM伴侶芯片VR4121TM
文件頁數(shù): 28/44頁
文件大小: 278K
代理商: UPD31172F1-48-FN
Data Sheet U14388EJ2V0DS00
28
μ
PD31172
(a)
Serial BAUDOUT timing
t
BHD
t
BLD
t
BHD
t
BLD
t
BLD
t
BLD
CLK
(internal, 1.8462 MHz)
BAUDOUTB
(1 cycle) (internal)
BAUDOUTB
(2 cycles) (internal)
BAUDOUTB
(3 cycles) (internal)
BAUDOUTB
(N cycles, N > 3)
(internal)
t
BHD
t
BHD
t
HW
t
LW
t
HW
t
HW
t
HW
t
LW
t
LW
t
LW
(b)
Serial receive timing
RCLK
(BAUDOUTB)
Internal sample clock
RXD (input)
Internal sample clock
INTRP (output)
(receive data existence interrupt
)
INTRP (output)
(receive status interrupt
)
IOR# (input)
(reading RBR register)
IOR# (input)
(reading LSR register)
t
SINT
t
RINT2
t
SCD
8 RCLKC
Start bit
Stop bit
Parity bit
DATA (5:8)
16 RCLKC
t
RINT1
Notes 1.
Dependant on the existence of receive data. At this time, bit 0 of the IER register is 1, and bits 3 to
1 of the IIR register are 0, 1, 0, respectively.
2.
Dependant on the receive line status. At this time, bit 2 of the IER register is 1, and bits 3 to 1 of the
IIR register are 0, 1, 1, respectively.
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