參數(shù)資料
型號： UPD31172F1-48-FN
廠商： NEC Corp.
英文描述： VRC4172TM COMPANION CHIP FOR VR4121TM
中文描述： VRC4172TM伴侶芯片VR4121TM
文件頁數(shù)： 27/44頁
文件大?。?/td> 278K
代理商： UPD31172F1-48-FN
Data Sheet U14388EJ2V0DS00
27
μ
PD31172
(9)
16550-compatible serial interface parameters
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transmit clock division ratio
N
1
2
16
1
Transmit clock rising edge delay time (from CLK
Note 1
)
t
BHD
10
ns
Transmit clock falling edge delay time (from CLK
Note 1
)
t
BLD
15
ns
N = 1
0.5CLKC
ns
N = 2
1CLKC
ns
N = 3
2CLKC
ns
Transmit clock pulse low-level width
t
LW
N
>
3
2CLKC
ns
N = 1
0.5CLKC
ns
N = 2
1CLKC
ns
N = 3
1CLKC
ns
Transmit clock pulse high-level width
t
HW
N
>
3
(N
2)
CLKC
ns
Interrupt cancellation time (from IOR#
↑
, when reading
LSR register)
t
RINT1
40
ns
Interrupt cancellation time (from IOR#
↓
, when reading
RBR register)
t
RINT2
30
ns
Sample clock delay time (from RCLK)
t
SCD
10
ns
Interrupt generation time (from valid data reception,
reception error)
t
SINT
1 RCLKC
+ 20
Note 2
ns
Interrupt cancellation time (from IOW#
↓
, when writing to
THR register)
t
HR
30
ns
Interrupt cancellation time (from IOR#
↑
, when reading
IIR register)
t
IR
40
ns
Transmission start time
t
IRS
8 BAUC
24 BAUC
+ 20
ns
Interrupt generation time (from IOW#
↑
, when writing to
THR register)
t
SI
16 BAUC
24 BAUC
+ 20
ns
Interrupt generation time (from stop bit)
t
STI
8 BAUC +
20
ns
RTS#, DTR delay time (from IOW#
↑
, when writing to
MCR register)
t
MDO
30
ns
Interrupt cancellation time (from IOR#
↓
, when reading
MSR register)
t
RIM
30
ns
Interrupt cancellation time (from RI#
↑
, CTS#, DSR#,
DCD#)
t
SIM
30
ns
Notes 1.
CLK is the internal system clock of the 16550 serial controller, and has a frequency of 1.8462 MHz.
2.
When bit 0 of the FCR register is 1, t
SINT
= 3 RCLKC + 20 (ns).
During a timeout interrupt, t
SINT
= 8 RCLKC + 20 (ns).
Remark
CLKC:
CLK (internal system clock of 16550 serial controller) cycle
RCLK (on-chip serial controller receive clock) cycle
BAUDOUTB (on-chip serial controller transmit clock) cycle
RCLKC = BAUC in this case.
RCLKC:
BAUC:
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