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μ
PD17016, 17017
91
11.3.2 Function of timer carry
The timer carry is set to 1 at the rising edge of the timer carry FF setting pulse that is set by the low-order
2 bits (BTM0CK1 and BTM0CK0 flags) of the timer mode select register.
The content of the timer carry FF corresponds to the least significant bit (BTM0CY flag) of the timer carry
FF judge register (RF address 17H) on a one-to-one basis. If the timer carry FF is set to “1”, therefore, the
BTM0CY flag is also set to “1”.
The BTM0CY flag is reset to “0” when data is written to the window register by the “PEEK” instruction (Read
& Reset).
When the BTM0CY flag is reset to “0”, the timer carry FF is also reset to “0”.
Therefore, a timer that is set via the timer mode select register can be used by reading the contents of the
BTM0CY flag by program.
When using the timer carry, note the following.
Caution
The timer carry is disabled from being set on application of the supply voltage V
DD
(on power-
ON reset), and is not set to “1” until the content of the BTM0CY flag is once read by the “PEEK”
instruction.
This means that “0” is always read from the BTM0CY flag immediately after power-ON reset, and that the
flag is set to “1” at time intervals set by the timer mode select register.
The timer carry also controls the timing of the reset operation by the CE pin (CE reset). If the CE pin goes
high, CE reset is effected in synchronization with the timing that sets the timer carry FF to “1”.
Therefore, a power failure can be detected by reading the content of the BTM0CY flag at system reset (power-
ON reset and CE reset).
For details, refer to
11.3.7 Notes on using timer carry
.
Because the BTM0CY flag is a read-only flag, the device operation is not affected in any way even if data
is written to this flag by using the “POKE” instruction. However, an error occurs if the 17K Series assembler
is used.
For details, refer to
8.4 Notes on Using Register File
.