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μ
PD17016, 17017
80
10.6 Acknowledging Interrupts
10.6.1 Acknowledging interrupts and priority
An interrupt is acknowledged in the following procedure:
(1) Each peripheral hardware unit outputs an interrupt request signal to the corresponding interrupt control block
if a given interrupt condition is satisfied (e.g., if a rising signal is input to the INT
0
pin).
(2) When the interrupt control block has received the interrupt request signal from the peripheral hardware unit,
it sets the corresponding interrupt request flag (e.g., IRQ0 flag if the peripheral unit is the INT
0
pin) to “1”.
(3) If the interrupt permission flag corresponding to the interrupt request flag (e.g., IP0 flag for IRQ0 flag) is set
to “1” when the interrupt request flag is set to “1”, the interrupt control block outputs “1”.
(4) The signal output by the interrupt control block is ANDed with the output of the interrupt enable flip-flop, and
an interrupt acknowledge signal is output.
This interrupt enable flip-flop is set to “1” by the “EI” instruction and reset to “0” by the “DI” instruction.
If the interrupt control block outputs “1” while the interrupt enable flip-flop is “1”, the interrupt is acknowledged.
As shown in Figure 10-1, the interrupt acknowledge signal is input to each interrupt control block when the
interrupt has been acknowledged.
The interrupt request flag is reset to “0” by the signal input to the interrupt control block, and a vector address
corresponding to the interrupt is output.
If more than one interrupt block outputs “1” at this time, the interrupt acknowledge signal is not transferred
to the next stage. If more than one interrupt request is issued at the same time, therefore, the interrupts are
acknowledged in the following priority.
INT
0
pin > timer
The interrupt of an interrupt source is not acknowledged unless the corresponding interrupt permission flag
is set to “1”.
If the interrupt permission flag is reset to “0”, therefore, an interrupt with a high hardware priority can be
disabled.