參數(shù)資料
型號(hào): UDA1342
廠商: NXP Semiconductors N.V.
元件分類: Codec
英文描述: Audio CODEC
中文描述: 音頻編解碼器
文件頁(yè)數(shù): 33/44頁(yè)
文件大?。?/td> 180K
代理商: UDA1342
2000 Mar 29
33
Philips Semiconductors
Preliminary specification
Audio CODEC
UDA1342TS
Notes
1.
2.
The typical value of the timing is specified at 48 kHz sampling frequency.
In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
small as possible.
When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to
1
64fs
cycle.
C
b
is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
After this period, the first clock pulse is generated.
To be suppressed by the input filter.
3.
4.
5.
6.
t
stp(L3)
L3MODE stop time in data
transfer mode
L3DATA set-up time in address
and data transfer mode
L3DATA hold time in address and
data transfer mode
L3DATA set-up time for read data
L3DATA hold time for read data
L3DATA enable time for read data
L3DATA disable time for read data
190
ns
t
su(L3)DA
190
ns
t
h(L3)DA
30
ns
t
su(L3)R
t
h(L3)R
t
en(L3)R
t
dis(L3)R
50
360
380
50
ns
ns
ns
ns
I
2
C-bus interface timing
(see Fig.15)
f
SCL
t
LOW
t
HIGH
t
r
t
f
t
HD;STA
t
SU;STA
t
SU;STO
t
BUF
SCL clock frequency
SCL LOW time
SCL HIGH time
rise time SDA and SCL
fall time SDA and SCL
hold time START condition
set-up time repeated START
set-up time STOP condition
bus free time between a STOP
and START condition
data set-up time
data hold time
pulse width of spikes
capacitive load for each bus line
0
1.3
0.6
20 + 0.1C
b
20 + 0.1C
b
0.6
0.6
0.6
1.3
400
300
300
kHz
μ
s
μ
s
ns
ns
μ
s
μ
s
μ
s
μ
s
note 4
note 4
note 5
t
SU;DAT
t
HD;DAT
t
SP
C
b
100
0
0
50
400
ns
μ
s
ns
pF
note 6
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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