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參數(shù)資料
| 型號： | UDA1324TS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | Ultra low-voltage stereo filter DAC |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 107K |
| 代理商： | UDA1324TS |
2000 Jan 20
9
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
handbook, full pagewidth
tstp(L3)
address
L3DATA
L3CLOCK
L3MODE
address
data byte #1
data byte #2
MGL725
Fig.6 Multibyte data transfer.
Programming the features
When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format
can be controlled.
Table 6
Data transfer of type ‘status’
When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled.
Table 7
Data transfer of type ‘data’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
0
SC1
SC0
IF2
IF1
IF0
0
SC = system clock frequency (2 bits); see Table 8
IF = data input format (3 bits); see Table 9
not used
1
0
0
0
0
0
0
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
0
1
0
1
0
VC5
0
0
VC4
0
DE1
VC3
0
DE0
VC2
0
MT
VC1
0
0
VC0
0
0
VC = volume control (6 bits); see Table 11
not used
DE = de-emphasis (2 bits); see Table 10
MT = mute (1 bit); see Table 12
default setting
1
1
0
0
0
0
0
1
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