2000 Jan 20
2
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
FEATURES
General
Low power consumption
Ultra low power supply voltage from 1.9 to 2.7 V
Selectable control via L3 microcontroller interface or via
static pin control
System clock frequencies of 256f
s
, 384f
s
and 512f
s
selectable via L3 interface or 256f
s
and 384f
s
via static
pin control
Supports sampling frequencies (f
s
) from 16 to 48 kHz
Integrated digital filter plus non inverting
Digital-to-Analog Converter (DAC)
No analog post filtering required for DAC
Slave mode only applications
Easy application
Small package size (SSOP16).
Multiple format input interface
L3 mode: I
2
S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible
Static pin mode: I
2
S-bus or LSB-justified
16, 18 and 20 bits format compatible
1f
s
input format data rate.
DAC digital sound processing
Digital logarithmic volume control in L3 mode
Digital de-emphasis selection for 32, 44.1 and 48 kHz
sampling frequencies in L3 mode or 44.1 kHz sampling
frequency in static pin mode
Soft mute control in static pin mode or in L3 mode.
Advanced audio configuration
Stereo line output (volume control in L3 mode)
High linearity, wide dynamic range and low distortion.
APPLICATIONS
Portable digital audio equipment.
GENERAL DESCRIPTION
The UDA1324TS is a single-chip stereo DAC employing
bitstream conversion techniques. The ultra low-voltage
requirements make the device eminently suitable for use
in portable digital audio equipment which incorporates
playback functions.
The UDA1324TS supports the I
2
S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
serial data format with word lengths of 16, 18 and 20 bits.
The UDA1324TS can be used in two modes: L3 mode or
static pin mode.
In the L3 mode, all digital sound processing features must
becontrolledviatheL3 interface,includingtheselectionof
the system clock setting.
In the two static modes, the UDA1324TS can be operated
in the 256f
s
and 384f
s
system clock mode. Muting,
de-emphasis for 44.1 kHz and four digital input formats
(I
2
S-bus or LSB-justified 16, 18 and 20 bits) can be
selected via static pins. The L3 interface cannot be used in
this application mode, so volume control is not available in
this mode.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1324TS
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1