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參數(shù)資料
| 型號： | UDA1324TS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | Ultra low-voltage stereo filter DAC |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 107K |
| 代理商： | UDA1324TS |
2000 Jan 20
13
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
TIMING
V
DDD
= V
DDA
= 1.9 to 2.7 V; T
amb
=
40 to +85
°
C; R
L
= 5 k
; all voltages referenced to ground (pins V
SSA
and V
SSD
);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock
(see Fig.7)
T
sys
system clock cycle time
f
sys
= 256f
s
f
sys
= 384f
s
f
sys
= 512f
s
f
sys
< 19.2 MHz
f
sys
≥
19.2 MHz
f
sys
< 19.2 MHz
f
sys
≥
19.2 MHz
78
52
39
0.3T
sys
0.4T
sys
0.3T
sys
0.4T
sys
88
59
44
244
162
122
0.7T
sys
0.6T
sys
0.7T
sys
0.6T
sys
ns
ns
ns
ns
ns
ns
ns
t
CWL
LOW-level system clock pulse width
t
CWH
HIGH-level system clock pulse width
Digital interface with I
2
S-bus
(see Fig.8)
T
cy(BCK)
t
BCKH
t
BCKL
t
r
t
f
t
su(DATAI)
t
h(DATAI)
t
su(WS)
t
h(WS)
Control L3 interface
(see Figs 4 and 5)
bit clock cycle time
bit clock HIGH time
bit clock LOW time
rise time
fall time
data input set-up time
data input hold time
word select set-up time
word select hold time
300
100
100
20
0
20
10
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
cy(CLK)L3
t
CLK(L3)H
t
CLK(L3)L
t
su(L3)A
t
h(L3)A
t
su(L3)D
L3CLOCK cycle time
L3CLOCK HIGH time
L3CLOCK LOW time
L3MODE set-up time for address mode
L3MODE hold time for address mode
L3MODE set-up time for data transfer
mode
L3MODE hold time for data transfer
mode
L3DATA set-up time for data transfer and
address mode
L3DATA hold time for data transfer and
address mode
L3MODE stop time for data transfer
mode
500
250
250
190
190
190
ns
ns
ns
ns
ns
ns
t
h(L3)D
190
ns
t
su(L3)DA
190
ns
t
h(L3)DA
30
ns
t
stp(L3)
190
ns
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