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參數(shù)資料
| 型號： | UDA1324TS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | Ultra low-voltage stereo filter DAC |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 107K |
| 代理商： | UDA1324TS |
2000 Jan 20
4
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
PINNING
FUNCTIONAL DESCRIPTION
System clock
The UDA1324TS operates in the slave mode only.
Therefore, in all applications the system devices must
provide the system clock. The system frequency (f
sys
) is
selectable and depends on the application mode.
The options are: 256f
s
, 384f
s
and 512f
s
for the L3 mode
and 256f
s
or 384f
s
for the static pin mode. The system
clock must be locked in frequency to the digital interface
input signals.
The UDA1324TS supports sampling frequencies (f
s
) from
16 to 48 kHz.
Application modes
The application mode can be set with the three-level
pin APPSEL (see Table 1):
L3 mode
Static pin mode with f
sys
= 384f
s
Static pin mode with f
sys
= 256f
s
.
Table 1
Selecting application mode and system clock
frequency via pin APPSEL
The function of an application input pin (active HIGH)
depends on the application mode (see Table 2).
Table 2
Functions of application input pins
For example, in the static pin mode the output signal can
be soft muted by setting pin APPL0 to HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
pin APPL1 to HIGH; setting pin APPL1 to LOW will disable
de-emphasis.
SYMBOL
PIN
DESCRIPTION
BCK
WS
DATAI
V
DDD
V
SSD
SYSCLK
1
2
3
4
5
6
bit clock input
word select input
data input
digital supply voltage
digital ground
system clock input: 256f
s
, 384f
s
and 512f
s
application mode select input
application input pin 3
application input pin 2
application input pin 1
application input pin 0
DAC reference voltage
analog supply voltage for DAC
left channel output
analog ground for DAC
right channel output
APPSEL
APPL3
APPL2
APPL1
APPL0
V
ref(DAC)
V
DDA
VOUTL
V
SSA
VOUTR
7
8
9
10
11
12
13
14
15
16
Fig.2 Pin configuration.
handbook, halfpage
UDA1324TS
MBK769
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUTR
BCK
VSSA
WS
VOUTL
DATAI
VDDA
VDDD
Vref(DAC)
VSSD
APPL0
SYSCLK
APPL1
APPSEL
APPL2
APPL3
VOLTAGE ON
PIN APPSEL
MODE
f
sys
V
SSD
0.5V
DDD
V
DDD
L3 mode
256f
s
, 384f
s
or 512f
s
384f
s
256f
s
static pin mode
PIN
FUNCTION
L3 MODE
STATIC PIN MODE
APPL0
APPL1
APPL2
APPL3
TEST
L3CLOCK
L3MODE
L3DATA
MUTE
DEEM
SF0
SF1
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