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參數(shù)資料
| 型號(hào)： | UCC2941-ADJ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1V Synchronous Boost Converter |
| 中文描述： | 1V的同步升壓轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | UCC2941-ADJ |
4
UCC19411/2/3
UCC29411/2/3
UCC39411/2/3
PIN DESCRIPTIONS
VIN:
Input Voltage to supply the IC during start-up. After
the output is running the IC draws power from VOUT or
VGD.
SW:
An inductor is connected between this node and
VIN. The VGD (Gate Drive Supply) flyback diode is also
connected to this pin. When servicing the main output
supply this pin will pull low charging the inductor, then
shut off dumping the energy through the synchronous
rectifier to the output. When servicing the VGD supply
the internal synchronous rectifier stays off and the en-
ergy is diverted to VGD through the flyback diode. During
discontinuous portions of the inductor current, a MOS-
FET resistively connects VIN to SW damping excess cir-
culating energy to eliminate undesired high frequency
ringing.
VGD:
The VGD pin which is coarsely regulated around
7V (8.5V for the UCC39413) is primarily used for the
gate drive supply for the power switches in the IC. This
pin can be loaded with up to 10mA as long as it does not
present a load at voltages below 2V (this ensures proper
start-up of the IC). The VGD supply can go as low as
6.3V without interfering with the servicing of the main
output. Below 6.3V, VGD will have the highest priority.
VOUT:
Main output voltage (3.3V, 5V, or adjustable)
which has highest priority in the multiplexing scheme, as
long as VGD is above the critical level of 6.3V. Startup at
full load is achievable at input voltages down to 1V.
CT:
This pin provides the timer for determining the reset
period. The period is controlled by placing a capacitor to
ground of value C = (0.81e
-6
)
T where T is the desired
reset period.
RESB:
This pin provides an active low signal to alert the
user when the main output voltage falls below 10% of its
targeted value. The open drain output can be used to re-
set a microcontroller which may be powered off of the
main output voltage.
SD/FB:
For the UCC39411, this pin is used to adjust the
output voltage via a resistive divider from VOUT. It also
serves as the shutdown pin for all three versions. Pulling
this pin low provides a shutdown signal to the IC.
GND:
Ground of the IC.
APPLICATION INFORMATION
Operation
A detailed block diagram of the UCC39411 is shown in
Figure 1. Unique control circuitry provides high efficiency
power conversion for both light and heavy loads by tran-
sitioning between discontinuous and continuous conduc-
tion based on load conditions.
converter waveforms for the application circuit shown in
Figure 3.
A single 22
μ
H inductor provides the energy
pulses required for a highly efficient 3.3V converter at up
to 200mW output power
Figure 2 depicts
At time t1 the 3.3V output voltage has dropped below its
lower threshold, and the inductor is charged with an on
time determined by: T
ON
= 5.5
μ
s/VIN. For a 1.25V input
and a 22
μ
H inductor, the resulting peak current is ap-
proximately 250mA. At time t2, the inductor begins to
discharge with a minimum off time of approximately 1
μ
s.
Under lightly loaded conditions, the amount of energy
delivered in this single pulse would satisfy the voltage
control loop, and the converter would not command any
more energy pulses until the output again drops below
the lower voltage threshold
At time t3 the VGD supply drops below its lower thresh-
old, but the output voltage is still above its threshold
point. This results in an energy pulse to the gate drive
supply at t4. In some cases, a single pulse supplied to
VGD is insufficient to raise the VGD voltage level enough
to satisfy the voltage loop. Under this condition, multiple
pulses will be supplied to VGD.
UCC39411/2/3 is servicing VGD only, the IC will maintain
a discontinuous mode of operation.
3.3V output drops below its threshold and requests to be
serviced once the VGD cycle has completed, which oc-
curs at time t5.
Note: when the
After time t4, the
Time t6 represents a transition between light load and
heavy load.
A single energy pulse is not sufficient to
force the output voltage above its upper threshold before
the minimum off time has expired and a second charge
cycle is commanded.
Since the inductor current does
not reach zero in this case, the peak current is greater
than 250mA at the end of the next charge on time. The
result is a ratcheting of inductor current until either the
output voltage is satisfied, or the converter reaches its
set current limit. At time t7, the gate drive voltage has
dropped below its 7V threshold but the converter contin-
ues to service the output because it has higher priority
unless VGD drops below
≈
6.3V
Between time t7 and t8, the converter reaches its peak
current limit.
Once the peak current is reached, the converter oper-
ates in continuous mode with approximately 60mA of in-
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