Philips Semiconductors
Preliminary specification
UCB1100
Advanced modem/audio analog front-end
1998 May 08
8
6.0
The UCB1100 consists of several analogue and digital sub circuits
which can be programmed via the Serial Interface Bus (SIB). This
enables the user to set the UCB1100 functionality according actual
application requirements.
FUNCTIONAL DESCRIPTION
6.1
The audio codec contains an input channel, built up from a 64 times
oversampling sigma delta analogue to digital converter (ADC) with
digital decimation filters and a programmable gain microphone
preamp. The output path consists of a digital up sample filter, a 64
time oversampling 4 bit digital to analogue converter (DAC) circuit
followed by a speaker driver, capable of driving directly a low
impedance bridge tied (BTL) speaker. The output path features
digitally programmable attenuation and a mute function. The audio
codec also incorporates a loopback mode, in which codec output
path and the input path are connected in series.
Audio codec
The audio sample rate is derived from the SIB interface clock pin
(SIBclk) and is programmable through the SIB interface. The audio
sample rate is given by the following equation:
Fsa
(2 * Fsibclk)
(64 * audio_divisor)
(5
audio_divisor
128)
For example, a serial clock of 10 MHz, with a divisor of 14, results in
an audio sample rate of 22.321kHz. Both the rising and the falling
edges of the sibclk are used in case an odd audio_divisor is set.
Thus a 50% duty cycle of the sibclk signal is mandatory to obtain
time equidistant sampling with odd divisors.
The frequency response of the audio codec depends mainly on the
selected sample rate, since the bandwidth is limited in the down and
up sampling filters. These digital filters both contain several FIR and
IIR low pass filters and a DC removal filter (high pass filter). A 1st
order analogue anti aliasing filter is implemented at the input of the
microphone input to prevent aliasing in the adc path. A 3rd order
smoothing filter is implemented between dac and speaker driver
stage to reduce the spurious frequencies at the speaker outputs.
The audio codec input (=ADC) and output (= DAC) paths can be
enabled individually by setting the audio_adc and/or audio_dac bits
in the audio control register B. These enable bits operate both on
the associated analogue and digital functions, for optimal power
control of both the analogue and the digital parts.
vdda2
vssa2
spkrp
spkrn
mute
4 bit DAC
64fsa
4
64fs
digital
volume
control
audio_output_enable
attn[4,5]
attn[0,3]
loopback
mux
gain[0,2]
1 bit ADC
64fsa
1
64fs
audio_input_enable
gain[3,4]
vssa1
micgnd
micp
loop input
FIR
16
reDC
hWDF
2
hWDF
2
+3dB
round
up
12
fs
haFIR
2
round
up
hWDF
2
+3dB
2
reDC
12
fs
loFIR
2
interpolator
loop input
noise
shaper
4
SN00128
Figure 3.
Detailed Block Diagram Audio codec