
Philips Semiconductors
Preliminary specification
UCB1100
Advanced modem/audio analog front-end
1998 May 08
20
The ADC sequence is started in two ways. First it starts whenever
the adc_startbit in register 10 is changed from ‘0’ to ‘1’; this is the
case when the adc_sync_enabit in registers 10 equals ‘0’
(=default). Internal logic determines whether the adc input
multiplexer setting was changed in the sib frame, carrying the
adc_start bit transition. If this is the case, an additional tracking time
is added automatically.
The second mode of operation is activated when the adc_sync_ena
bit is set to ‘1’. In this mode the ADC conversion is not started by an
‘0’ to ‘1’ transition of the adc_startbis, but is ‘a(chǎn)rmed’. During the
arming situation the track and hold circuit tracks the selected input
signal. A sample is taken and the actual ADC conversion is started
when a rising edge is detected on the adcsync input pin.
The internal ADC start logic adds a fixed tracking time, when the
ADC input multiplexer was changed in the SIB frame with the ‘0’ to
‘1’ transition of the adc_start bit. A rising edge on the adcsync pin
will not have any effect during this tracking time; the ADC sequence
will start on the first detected rising edge on the adcsyn pin after this
tracking time.
This mode is particulary useful when the internal ADC has to be
synchronized with the external systems. Typically it is used to
synchronize the readout of the touch screen with the driving of the
LCD screen, which is normally placed in the direct neighborhood of
the touch screen. Many spikes and a lot of ‘noise’ are superposed
on the touch screen signals, due to the close coupling of the touch
screen and the LCD.
The UCB1100 contains four high voltage analogue inputs ad0–3
which can be selected by the ADC input multiplexer, besides the
already discussed touch screen interface signals. These high
voltage inputs optimized to handle voltages larger than the applied
supply voltage. The built in resistive voltage divider are only
activated if the corresponding analogue input is selected. The not
selected ad0–3 inputs are high ohmic resulting in minimal leakage
input leakage of these pins.
tadcena
tadctrk
tadcdead
tadcstrs
tadccal
tconv
track
cal
conversion
adc_ena
adc_input_selection
adc_start
adcsync
’adc state’
adc_dat_valid
adc_data
SN00146
Figure 21.
Timing Diagram of an ADC Conversion Sequence (adc_sync_ena=‘1’)
adc_inp_sel[2:0]
ad0 or ad1 or ad2 or ad3
adc
input
switch
SN00147
Figure 22.
ad0–ad3 Resistive dividers