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參數(shù)資料
| 型號(hào)： | UCB1100LP |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Advanced modem/audio analog front-end |
| 中文描述： | 先進(jìn)的調(diào)制解調(diào)器/音頻模擬前端 |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 290K |
| 代理商： | UCB1100LP |
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Philips Semiconductors
Preliminary specification
UCB1100
Advanced modem/audio analog front-end
1998 May 08
22
6.7
The UCB1100 serial interface bus (SIB) is compatible with industry
standard serial ports and devices, and is designed to connect
directly to a system controller. The sib protocol allows one or more
slave devices to be connected to the system controller. The data
transfer is always synchronous and it is frame based. The SIB
interface consists of four signals: sibddn, sibdout, sibclk and
sibsync.
Serial Interface Bus
Each SIB frame consists of at least 64 clock cycles. Typically 128
bits are used, divided into 2 sub frames of 64 bits each. The first
word (the bits 0 to 63) is read and/or written by the UCB1100, the
remaining bits may be used for communication between the system
controller and another slave device. The sibdout pin of the UCB1100
is default-stated for the bit 64 and higher in the SIB frame to prevent
bus conflicts with other slave devices. However when the
sib_zero_ena bit (control register 1) is set, the sibdout pin is forced
to zero for bit 64 and higher to prevent floating of the sibdout line
during this part of the sib frame in case when the UCB1100 is the
only slave device connected to the bus.
The UCB1100 always samples incoming data on the sibdin pin on
the falling edge of sibclk and it outputs data on the sibdout pin on
the rising edge of the sibclk. The start of a new sib frame is indicated
by a pulse on the sibsync line just before the start of this new sib
frame.
The applied clock signal to the sibclk pin is used as clock signal
inside the UCB1100; all internal clock signals are derived from that.
It is required that the sibclk signal is applied if one or more analogue
or digital functions is activated in the UCB1100; only the interrupt
controller is implemented synchronously. The sibclk may be stopped
when all digital and analogue functions are disabled; in that case the
lowest possible power consumption is meet. The sibclk should not
be stopped during a sib frame, but only at the end of the sib-frame,
to ensure that all analogue and digital functions are stopped
properly.
NOTE:
The interrupt controller is still active, due to its
asynchronous implementation. The UCB1100 can
therefore still generate interrupts to the system controller,
when the sibclk is stopped.
The generation of the audio and telecom sample clocks require that
the sibclk signal is symmetrical: a non symmetrical sibclk will lead to
non equidistant sample moments, when an odd frequency divisor is
set in either of the audio or telecom control registers.
sibclk
sibdin
sibdout
sibsync
sibclk
sibsync
sibdin
sibdout
sibclk
sibsync
sibdin
sibdout
SIB MASTER
UCB11001
SIB SLAVE 2
TO OTHER SIB SLAVES
SN00149
Figure 24.
Typical Connection Between the UCB1100 and the
System Controller
bit 0
bit 1
bit 2
bit 3
bit 63
bit 62
bit 64
bit 65
bit 126
bit 0
bit 127
sibclk
sibsync
sibdin
sibdout #1
sibdout #2
SN00150
Figure 25.
Serial Data Transmission of the UCB1100,
sibdout #1 in case sib_zero bit = ‘0’, sibdout #2 in case sib_zero bit = ‘1’
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