參數(shù)資料
型號: UCB1100
廠商: NXP Semiconductors N.V.
英文描述: Advanced modem/audio analog front-end
中文描述: 先進(jìn)的調(diào)制解調(diào)器/音頻模擬前端
文件頁數(shù): 21/36頁
文件大小: 290K
代理商: UCB1100
Philips Semiconductors
Preliminary specification
UCB1100
Advanced modem/audio analog front-end
1998 May 08
21
6.5.1
Specification Overview
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
MIN
TYP
MAX
RES
ADC
V
FSad
R
INad
resolution of ADC
10
bit
full scale ad0–3 inputs
7.17
7.5
7.9
V
input impedance selected ad0–3 pin
50
75
I
Lad
input leakage current,
non selected ad0–3 pins
<1
10
μ
A
DNL
ADC
INL
ADC
t
conv
t
adccal
differential non-linearity
0.1
0.5
lsb
integral non linearity
0.5
2
lsb
conversion time
110
t
sibclk
t
sibclk
settling time
10
tracking time
no adc input change
adc input change
adc_sync_ena=‘0’
t
adctrk
1
t
sibclk
t
sibclk
50
tracking time
no adc input change
adc input change
adc_sync_ena=‘1’
t
adctrks
25
ns
50
t
sibclk
ns
t
hadcsync
t
padcsync
10
6.6
The UCB1100 contains an on chip reference voltage source, which
generates the reference voltages for the 10 bit ADC and the
necessary internal reference voltages. Alternatively, the UCB1100
can be driven from an external reference voltage source.
On Chip Reference Circuit
The internal reference voltage can be monitored and filtered
additionally on the vrefbyp pin. Two bits in the ADC control register
determine the mode of operation of this reference voltage circuit.
The vrefbyp_conbit connects the internal reference voltage to the
vrefbyp pin, while the ext_vref_enabit disables the internal
reference voltage and switches the UCB1100 into the external
voltage reference mode.
The internal reference circuit is activated only when one or more
analogue functions inside the UCB1100 is activated. This reduces
the current consumption of the analogue part in standby mode. The
external reference voltage source is also disconnected when all
analogue functions are disabled.
Internal
reference
circuitry
ext_vref_ena
vrefbyp_con
vrefbyp
internal
reference
voltage
aud_in_ena
aud_out_ena
tel_in_ena
tel_out_ena
tsc_bias_ena
adc_ena
&
&
SN00148
Figure 23.
Block Diagram of the Reference Circuit
6.6.1
Specification Overview
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
MIN
TYP
MAX
V
REF
reference voltage
1.1
1.2
1.3
V
t
refstrt
start up time of internal reference voltage
circuit
50
t
sibclk
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