
Low Power CMOS SRAM
256K X 16
UC62LV4096
-55/-70
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
AC TEST LOADS AND WAVEFORMS
3.3V
INCLUDING
JIG AND
SCOPE
VCC to 0V
1V/ns
0.5V
CC
OUTPUT
1
1
1
FIGURE 1A
3.3V
OUTPUT
1
1
5
INCLUDING
JIG AND
SCOPE
FIGURE 1B
667
TERMINAL EQUIVALENT
OUTPUT
1.73V
GND
V
CC
1V/ns
1V/ns
10%
90%
90%
10%
ALL INPUT PULSES
FIGURE 2
AC ELECTRICAL CHARACTERISTICS (TA=0
READ CYCLE
JEDEC
PARAMETER
NAME
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE
STATE
UNKNOWN
DOES NOT
APPLY
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
to 70
, V
CC
=1.5 V~3.6V)
UC62LV4096-55
UC62LV4096-70
PARAMETER
NAME
DESCRIPTION
Min
Typ
Max
Min
Typ
Max
UNIT
t
AVAX
t
RC
Read Cycle Time
55
-
-
70
-
-
ns
t
AVQV
t
AA
Address Access Time
-
-
55
-
-
70
ns
t
ELQV
t
CE
Chip Select Access Time
-
-
55
-
-
70
ns
t
BA
t
BA
Data Byte Control Access Time
30
35
ns
t
GLQV
t
OE
Output Enable to Output Valid
-
-
30
-
-
35
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
10
-
-
10
-
-
ns
t
GLQX
t
OLZ
Output Enable to Output Low Z
5
-
-
5
-
-
ns
t
BE
t
BE
Data Byte Control To Output Low Z
10
10
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
-
-
20
-
-
20
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
-
-
20
-
-
20
ns
t
BDO
t
BDO
Data Byte Control To Output High Z
-
20
-
20
ns
t
AXOX
t
OH
Address Chang to Output Change
10
-
-
10
-
-
ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
PAGE
4
Preliminary
Rev. 1.0