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參數(shù)資料
| 型號(hào)： | UC62LV4096 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Low Power CMOS SRAM |
| 中文描述： | 低功耗CMOS SRAM |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | UC62LV4096 |
Low Power CMOS SRAM
256K X 16
UC62LV4096
-55/-70
PIN DESCRIPTION
Name
Type
Function
A0 – A17
Input
Address inputs for selecting one of the 262,144 x 16 bit words in the RAM
CE\
Input
CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip
enable is not active, the device is deselected and not in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
WE\
Input
The Write enable input is active LOW and controls read and write operations. With the chip
selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when
WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
OE\
Input
The output enable input is active LOW. If the output enable is active while the chip is selected
and the write enable is inactive, data will be present on the DQ pins and they will be enabled.
The DQ pins will be in the high impedance state when OE\ is inactive.
UB\ and LB\
Input
Lower byte and upper byte data input/output control pins.
DQ0 – DQ15
I/O
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power
Power Supply
Gnd
Power
Ground
TRUTH TABLE
Mode
WE\
CE\
OE\
LB\
UB\
I/O 0 ~ 7
I/O 8 ~ 15
Vcc Current
Not Selected
X
H
X
X
X
High Z
High Z
I
SB
,I
SB1
H
L
H
X
X
Output Disabled
X
L
X
H
H
High Z
High Z
I
CC
H
L
L
L
H
D
OUT
High Z
H
L
L
H
L
High Z
D
OUT
Read
H
L
L
L
L
D
OUT
D
OUT
I
CC
L
L
X
L
H
D
IN
High Z
L
L
X
H
L
High Z
D
IN
Write
L
L
X
L
L
D
IN
D
IN
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
PARAMETER
RATING
UNIT
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to V
CC
+0.5
V
T
BIAS
Temperature Under Bias
-40 to 125
T
STG
Storage Temperature
-50 to 150
PT
Power Dissipation
0.5
W
I
OUT
DC Output Current
10
mA
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may
affect reliability.
OPERATING RANGE
RANGE
AMBIENT
TEMPERATURE
V
CC
Commercial
0
to 70
1.5V ~ 3.6V
Industrial
-40
to 85
1.5V ~ 3.6V
CAPACITANCE
(1)
(TA=25
PARAMETERCONDITIONS MAX.
,f=1.0MHz)
SYMBOL
UNIT
CIN
Input
Capacitance
Input/Output
Capacitance
VIN=0V
6
pF
CDQ
VDQ
8
pF
1. This parameter is guaranteed and not 100% tested.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
PAGE
2
Preliminary
Rev. 1.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UC62LV4096AC-20 | Low Power CMOS SRAM |
| UC62LV4096AC-25 | Low Power CMOS SRAM |
| UC62LV4096AI-20 | Low Power CMOS SRAM |
| UC62LV4096AI-25 | Low Power CMOS SRAM |
| UC62LV4096JC-20 | Low Power CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UC62LV4096AC-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
| UC62LV4096AC-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
| UC62LV4096AI-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
| UC62LV4096AI-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
| UC62LV4096JC-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
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