
U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
1999 ~
2003
46
ES Specifications
P
OWER
-U
P
S
EQUENCE
UC1682 power-up sequence is simplified by built-in
“Power Ready” flags and the automatic invocation
of
System-Reset
command after
Power-ON-Reset
.
System programmers are only required to wait 5~
10 ms before the CPU starting to issue commands
to UC1682. No additional time sequences are
required between enabling the charge pump,
turning on the display drivers, writing to RAM or
any other commands. However, while turning on
V
DD
, V
DD2/3
should be started not later than V
DD
.
Delay allowance between V
DD
and V
DD2/3
is
illustrated as Figure 15-1.
P
OWER
-D
OWN
S
EQUENCE
To prevent the charge stored in capacitors C
BX+
,
C
BX–
, and C
L
from damaging the LCD, when V
DD
is
switched off, use Reset mode to enable the built-in
draining circuit and discharge these capacitors.
The draining resistor is 1K
for both V
LCD
and V
B+
.
It is recommended to wait
3
x
RC
for V
LCD
and
1.5
x RC
for V
B+
. For example, if C
L
is 15nF, then the
draining time required for V
LCD
is 0.5~1mS.
When internal V
LCD
is not used, UC1682 will
NOT
drain V
LCD
during RESET. System designers need
to make sure external V
LCD
source is properly
drained off before turning off V
DD
.
Turn on VDD
Set LCD Bias Ratio (BR)
Set Potential Meter (PM)
Set Display Enable
Wait 5~10 mS
Set OTPC[4]
( Ignore OTP value when “L” )
Figure 15:
Reference Power-Up Sequence
T
Wait
> 50 mS
Turn off VDD
Reset command
Wait ~1 mS
Figure 16:
Reference Power-Down Sequence
Figure 15-1:
Delay allowance and Power Off-On Sequence
T
Delay
> 0 s
V
DD2/3
> 2.4V
V
DD
> 1.8V
V
DD2/3
> V
DD
10
μ
S < T
1
, T
2
< 10 mS
T
1
T
2
T
f
< 10 mS