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參數(shù)資料
| 型號(hào)： | UC1682 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HIGH-VOLTAGE MIXED-SIGNAL IC |
| 中文描述： | 高電壓混合信號(hào)集成電路 |
| 文件頁(yè)數(shù)： | 12/70頁(yè) |
| 文件大?。?/td> | 1161K |
| 代理商： | UC1682 |
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U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
1999 ~
2003
10
ES Specifications
C
ONTROL
R
EGISTERS
UC1682 contains registers which control the chip operation. These registers can be modified by commands.
The following table is a summary of the control registers, their meanings and their default values.
Commands supported by UC1682 will be described in the next two sections. First, a summary table,
followed by a detailed instruction-by-instruction description.
Name:
The Symbolic reference of the register.
Note that, some symbol name refers to bits (flags) within another register.
Default:
Numbers shown in
Bold
font are default values after
Power-Up-Reset
and
System-Reset
.
Name
Bits
Default
Description
SL
7
0H
Scroll Line. Scroll the displayed image up by SL rows. The valid SL value is
between 0 (for no scrolling) and (79– 2xFL). Setting SL outside of this range
causes undefined effect on the displayed image.
FL
4
0H
Fixed Lines. The first FLx2 lines of each frame are fixed and are not
affected by scrolling (SL). When FL is non-zero, the screen is effectively
separated into two regions: one scrollable, one non-scrollable.
When partial display mode is activated, the display of these 2xFL lines is
also controlled by LC[0].
CR
7
0H
Return Column Address. Useful for cursor implementation.
CA
7
0H
Display Data RAM Column Address (counted in RGB triplet)
(Used in Host to Display Data RAM access)
RA
7
0H
Display Data RAM Row Address
(Used in Host to Display Data RAM access)
BR
2
3H
Bias Ratio. The ratio between V
LCD
and V
BIAS
.
00b: 5
10b: 8
Temperature Compensation (per
o
C)
00b: -0.05%
10b: -0.15%
01b: 7
11b: 9
TC
2
0H
01b: -0.10%
11b: -0.20%
PM
8
55H
Electronic Potentiometer to fine tune V
BIAS
and V
LCD
PM offset. The effective PM value PMV = PM+PMO-32. Make sure PMV
formula does not overflow or underflow. (Available only on OTP version).
PMO
6
20H
OM
2
–
Operating Modes (Read only)
10b: Sleep
01b: (Not used)
11b: Normal
00b: Reset
ID
1
PIN
Access the connected status of ID pin.
MSK
3
0H
R/G/B Write Data mask bits MSK[2:0] = {MR, MG, MB} (Default:
000b
)
0: Write
1: Block
RS
1
Reset in progress. Host Interface not ready
PC
4
DH
Power Control.
PC[1:0]: 00b: LCD:
U
9nF
10b: LCD: 12~16nF
PC[3:2]: 00b: External V
LCD
01b: LCD: 9~12nF
11b: LCD: 16~22nF
11b: Internal V
LCD
(Standard)
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| UC1682TFBZ | HIGH-VOLTAGE MIXED-SIGNAL IC |
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| UC1682TFBZ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1682THCZ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:HIGH-VOLTAGE MIXED-SIGNAL IC |
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| UC1682XFBZ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1682XHCZ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:HIGH-VOLTAGE MIXED-SIGNAL IC |
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