
U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
1999-2002
4
Revision 0.52
P
IN
D
ESCRIPTION
Name
Type
Pins
Description
M
AIN
P
OWER
S
UPPLY
V
DD
V
DD2
V
DD3
PWR
V
DD2
/V
DD3
is the analog V
DD
and it should be connected to the same
power source. V
DD
is the digital V
DD
and is connected to a voltage
source that is the same, or lower than V
DD2
/V
DD3
.
V
DD
supplies for digital logic and display data RAM.
V
DD2
supplies for V
LCD
and V
BIAS
generator, V
DD3
supplies for other
analog circuits.
Minimize the trace resistance for V
DD
and V
DD2
.
V
SS
V
SS2
GND
Ground. Connect V
SS
and V
SS2
to the shared GND pin.
Minimize the trace resistance for V
SS
and V
SS2
.
LCD P
OWER
S
UPPLY
V
B3+
V
B3–
V
B2+
V
B2–
V
B1+
V
B1–
V
B0+
V
B0–
PWR
LCD Bias Voltages. These are the voltage source to provide SEG
driving currents. These voltages are generated internally. Connect
capacitors of C
BX
value between V
BX+
and V
BX–
.
The resistance of these four traces directly affects the SEG driving
strength of the resulting LCD module. Minimize the trace resistance is
critical in achieving high quality image.
S
B3+
S
B3–
S
B2+
S
B2–
S
B1+
S
B1–
S
B0+
S
B0–
I
The sensor pins for C
BX
capacitors. Please connect these sensor pins
as closely to proper C
BX
pads as possible. These signals can tolerate
input resistance of up to 2K Ohm, so, narrow COF traces can be used.
However, the noise on these pins affects the accuracy of SEG driving
voltage level. To minimize noise caused by V
BX
-C
BX
charging current,
the trace resistance shared between V
BX+/-
and S
BX+/-
should be
minimized.
V
LCD-IN
V
LCD-OUT
PWR
Main LCD Power Supply. Connect these pins together.
A by-pass capacitor C
L
is optional. When C
L
is used, connect C
L
between V
LCD
and V
SS
, and keep the trace resistance under 300 Ohm.
N
OTE
Recommended capacitor values:
C
B
: ~100x LCD load capacitance or 1.5uF (2V), whichever is higher.
C
L
: 10nF ~ 50nF (16V) is appropriate for most applications.