- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381146 > UC1608 (Electronic Theatre Controls, Inc.) 128COM x 240SEG Matrix LCD Controller-Driver PDF資料下載
參數(shù)資料
| 型號： | UC1608 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128COM x 240SEG Matrix LCD Controller-Driver |
| 中文描述： | 128COM x 240SEG矩陣LCD控制器驅(qū)動器 |
| 文件頁數(shù)： | 22/42頁 |
| 文件大小： | 996K |
| 代理商： | UC1608 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
UC1608
128x240 Matrix LCD Controller-Drivers
(Revision 0.52 Preview)
19
H
OST
I
NTERFACE
As summarized in the table below, UC1608
supports two parallel bus protocols, in either 8-bit
of 4-bit bus width.
Designers can either use parallel bus to achieve
high data transfer rate.
Bus Type
Width
Access
BM[1:0]
WR0
D
D[3:0]
* Connect unused control pins and data bus pins to V
DD
or V
SS
8080
6800
8-bit
4-bit
8-bit
4-bit
Read/Write
00
10
11
01
___ __
WR
___ __
RD
_ _
R/W
EN
WR1
D[7:4]
Data
Data
–
Data
Data
–
C
Data
Data
Table 5:
Host interfaces Choices
P
ARALLEL
I
NTERFACE
The timing relationship between UC1608 internal
control signal RD, WR and their associated bus
actions are shown in the figure below.
The Display RAM read interface is implemented
as a two-stage pipe-line. This architecture
requires that, every time memory address is
modified, either in 8-bit mode or 4-bit mode, by
either
Set CA,
or
Set PA
command, a dummy
read cycle need to be performed before the
actual data can propagate through the pipe-line
and be read from data port D[7:0].
There is no pipeline in write interface of Display
RAM. Data is transferred directly from bus buffer
to internal RAM on the rising edges of write
pulses.
8-
BIT
& 4-
BIT
B
US
O
PERATION
UC1608 supports both 8-bit and 4-bit bus width.
The bus width is determined by pin BM[1].
4-bit bus operation exactly doubles the clock
cycles of 8-bit bus operation, MSB followed by
LSB, including the dummy read, which also
requires two clock cycles.
L
LSB
D
L
D
L+K
C
MSB
C
LSB
Dummy
D
C
D
C+1
M
MSB
M
LSB
L
L+K
L+K+1
C
C+1
C+2
C+3
M
D
L
D
L+K
Dummy
D
C
D
C+1
D
C+2
External
CD
___
WR
__
RD
D[7:0]
Internal
Write
Read
Data
Latch
Column
Address
Figure 5:
8 bit Parallel Interface & Related Internal Signals
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UC1608xFAC | 128COM x 240SEG Matrix LCD Controller-Driver |
| UC1608xGAC | 128COM x 240SEG Matrix LCD Controller-Driver |
| UC1682 | HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1682TFBZ | HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1682THCZ | HIGH-VOLTAGE MIXED-SIGNAL IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UC1608T-100 | 制造商:ECM 制造商全稱:ECM Electronics Limited. 功能描述:Power Inductors |
| UC1608T-101 | 制造商:ECM 制造商全稱:ECM Electronics Limited. 功能描述:Power Inductors |
| UC1608T-102 | 制造商:ECM 制造商全稱:ECM Electronics Limited. 功能描述:Power Inductors |
| UC1608T-150 | 制造商:ECM 制造商全稱:ECM Electronics Limited. 功能描述:Power Inductors |
| UC1608T-151 | 制造商:ECM 制造商全稱:ECM Electronics Limited. 功能描述:Power Inductors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。