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參數(shù)資料
| 型號： | UC1606XGAF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65COM x 132SEG Matrix LCD Controller-Driver |
| 中文描述： | 65COM x 132SEG矩陣LCD控制器驅(qū)動器 |
| 文件頁數(shù)： | 6/46頁 |
| 文件大?。?/td> | 895K |
| 代理商： | UC1606XGAF |
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U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
1999-2003
4
Product Specifications
P
IN
D
ESCRIPTION
Name
Type
Pins
Description
M
AIN
P
OWER
S
UPPLY
V
DD
V
DD2
V
DD3
PWR
V
DD2
/V
DD3
is the analog power supply and it should be connected to the
same power source. V
DD
is the digital power supply and it should be
connected to a voltage source that is no higher than V
DD2
/V
DD3
.
Minimize the trace resistance for V
DD
and V
DD2
/V
DD3
.
V
SS
V
SS2
GND
Ground. Connect V
SS
and V
SS2
to the shared GND pin.
Minimize the trace resistance for V
SS
and V
SS2
.
LCD P
OWER
S
UPPLY
V
B1+
V
B1–
V
B0+
V
B0–
PWR
LCD Bias Voltages. These are the voltage sources to provide SEG
driving currents. These voltages are generated internally. Connect
capacitors of C
BX
value between V
BX+
and V
BX–
.
The resistance of these four traces directly affects the SEG driving
strength of the resulting LCD module. Minimize the trace resistance is
critical in achieving high quality image.
V
LCD-IN
V
LCD-OUT
PWR
Main LCD Power Supply. Connect these pins together.
A by-pass capacitor C
L
is optional. When C
L
is used, connect C
L
between V
LCD
and V
SS
, and keep the trace resistance under 300 Ohm.
N
OTE
In COG applications, use one maximum width trace to connect V
DD
/V
DD2
/V
DD3
to the LCM pad to
minimize trace resistance. However, to avoid noise cross-coupling, insert a slit, 0.2~0.3mm long,
between V
DD
/V
DD2
/V
DD3
. Same treatment for V
SS
/V
SS2
.
Recommended capacitor values:
C
B
: 150 ~ 250x LCD load capacitance or 1.0uF (2V), whichever is higher.
C
L
: 5nF ~ 20nF (16V) is appropriate for most applications.
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