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參數(shù)資料
| 型號： | UC1606XGAF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65COM x 132SEG Matrix LCD Controller-Driver |
| 中文描述： | 65COM x 132SEG矩陣LCD控制器驅(qū)動器 |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 895K |
| 代理商： | UC1606XGAF |
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U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
1999-2003
20
Product Specifications
H
OST
I
NTERFACE
As summarized in the table below, UC1606
supports two 8-bit parallel bus protocols and two
serial bus protocols. Designers can choose either
the 8-bit parallel bus to achieve high data transfer
rate, or use serial bus to create compact LCD
modules and minimize connector pins.
Bus Type
PS[1:0]
CS[1:0]
CD
WR0
8080
10b
6800
11b
SPI (S8)
00b
SPI(S9)
01b
Chip Select
Control/Data
_ _
R/W
–
0
___ __
WR
___ __
RD
0
WR1
Access
D[7:0]
EN
0
0
Read/Write
8-bit bus (Tri-state)
* Connect unused control pins to V
DD
or V
SS.
Write Only
D0=SCK, D2=SDA
C
Table 4:
Host interfaces Choices
P
ARALLEL
I
NTERFACE
The timing relationship between UC1606 internal
control signal RD, WR and their associated bus
actions are shown in the figure below.
The Display RAM read interface is implemented as
a two-stage pipeline. This architecture requires that,
every time memory address is modified, either in
parallel mode or serial mode, by either
Set CA
or
Set PA
command, a dummy read cycle need to be
performed before the actual data can propagate
through the pipeline and be read from data port
D[7:0].
There is no pipeline in write interface of Display
RAM. Data is transferred directly from bus buffer to
internal RAM on the rising edges of write pulses.
L
LSB
D
L
D
L+K
C
MSB
C
LSB
Dummy
D
C
D
C+1
M
MSB
M
LSB
L
L+K
L+K+1
C
C+1
C+2
C+3
M
D
L
D
L+K
Dummy
D
C
D
C+1
D
C+2
External
CD
___
WR
__
RD
D[7:0]
Internal
Write
Read
Data
Latch
Column
Address
Figure 4:
Parallel Interface & Related Internal Signals
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