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參數(shù)資料
| 型號： | UC1606XGAF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65COM x 132SEG Matrix LCD Controller-Driver |
| 中文描述： | 65COM x 132SEG矩陣LCD控制器驅(qū)動器 |
| 文件頁數(shù)： | 23/46頁 |
| 文件大?。?/td> | 895K |
| 代理商： | UC1606XGAF |
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UC1606
65x132 Matrix LCD Controller-Drivers
Version 1.32
21
S
ERIAL
I
NTERFACE
UC1606 supports two serial modes, 4-wire mode
(PS=”LL”), and 3-wire mode (PS=”LH”). The mode
of interface is determined during power-up process
by the value of PS[1:0].
4-
WIRE
S
ERIAL
I
NTERFACE
(S8)
Only write operations are supported in 4-wire serial
mode. Pin CS[1:0] are used for chip select and bus
cycle reset. Pin CD is used to determine the
content of the data been transferred. During each
write cycle, 8 bits of data, MSB first, are latched on
eight rising SCK edges into an 8-bit data holder.
If CD=0, the data byte will be decoded as
command. If CD=1, this 8-bit will be treated as data
and transferred to proper address in the Display
Data RAM on the rising edge of the last SCK pulse.
Pin CD is examined when SCK is pulled low for the
LSB (D0) of each token.
CS1/0
SDA
SCK
CD
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
Figure 5.a:
4-wire Serial Interface (S8)
3-
WIER
S
ERIAL
I
NTERFACE
(S9)
Only write operations are supported in 3-wire serial
mode. Pin CS[1:0] are used for chip select and bus
cycle reset. On each write cycle, the first bit is CD,
which determines the content of the following 8 bits
of data, MSB first. These 8 command or data bits
are latched on rising SCK edges into an 8-bit data
holder. If CD=0, the data byte will be decoded as
command. If CD=1, this 8-bit will be treated as data
and transferred to proper address in the Display
Data RAM at the rising edge of the last SCK pulse.
By sending CD information explicitly in the bit
stream, control pin CD is not used, and should be
connected to either V
DD
or V
SS
.
The toggle of CS0 (or CS1) for each byte of
data/command is recommended but optional.
CS0
SDA
SCK
CD
D7
D6
D5
D4
D3
D2
D1
D0
CD
D7
D6
Figure 5.b:
3-wire Serial Interface (S9)
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