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參數(shù)資料
| 型號： | TWL1110TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | VOICE-BAND AUDIO PROCESSOR VBAPE |
| 中文描述： | 語音頻帶音頻處理器VBAPE |
| 文件頁數(shù)： | 7/37頁 |
| 文件大小： | 496K |
| 代理商： | TWL1110TQFP |
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TWL1110
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS103 – NOVEMBER 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description (continued)
DTMF gain MUX
The DTMF gain MUX selects the signal path and applies the appropriate gain setting. Therefore the device is
either in tone mode or in voice mode. When set in the voice mode, the gain is controlled by the auxiliary register
and is set to 0 dB or 6 dB. When set in the tone mode, the gain is from –12 dB to 12 dB in 6-dB steps which
is set by the volume control register. The gain setting is controlled by the RXPGA register. This will not create
any control contention since the device is working in one mode at a time.
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
μ
BGA
A1
TQFP
32
AVDD
AVSS
BUZZCON
I
Analog positive power supply
J1
8
I
Analog negative power supply (use for ground connection)
F9
19
O
Buzzer output, a pulse-density modulated signal to apply to external buzzer driver
DVDD
DVSS
EAR1ON
J6
13
I
Digital positive power supply
J7
14
I
Digital negative power supply
A6
27
O
Earphone 1 amplifier output (–)
EAR1OP
A4
29
O
Earphone 1 amplifier output (+)
EAR2O
A2
31
O
Earphone 2 amplifier output
EARVDD
EARVSS
MBIAS
A5
28
I
Analog positive power supply for the earphone amplifiers
A3, A7
30, 26
I
Analog negative power supply for the earphone amplifiers
B1
1
O
Microphone bias supply output, no decoupling capacitors
MCLK
C9
22
I
Master system clock input (2.048 MHz, digital)
MIC1P
C1
2
I
MIC1 input (+)
MIC1N
D1
3
I
MIC1 input (–)
MIC2P
E1
4
I
MIC2 input (+)
MIC2N
F1
5
I
MIC2 input (–)
MUXIN
H1
7
I
Analog MUX input
MUXOUT1
J2
9
I
Analog MUX output
MUXOUT2
J3
10
I
Analog MUX output
PCMI
J8
15
I
Receive PCM input
PCMO
J9
16
O
Transmit PCM output
PCMSYN
G9
18
I
PCM frame sync
PCMCLK
H9
17
I
PCM data clock
PLLVSS
PLLVDD
PWRUPSEL
A9
24
I
PLL negative power supply
A8
25
I
PLL digital power supply
E9
20
I
Selects the power-up default mode
Internal reference current setting terminal (use precision 100
-
k
resistor and no filtering
capacitors)
REXT
G1
6
I/O
RESET
D9
21
I
Active low reset
I2C-bus serial clock (this input is used to synchronize the data transfer from and to the
VBAP)
I2C-bus serial address/data input/output. This is a bidirectional terminal used to transfer
register control addresses and data into and out of the codec. It is an open
-
drain terminal
and therefore requires a pullup resistor to VDD (typical 10 k
for 100 kHz).
Ground return for bandgap internal reference (use for ground connection)
SCL
J5
12
I
SDA
J4
11
I/O
VSS
All MicroStar Junior BGA pins that are not mentioned have no internal connection.
B9
23
I
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