參數(shù)資料
型號(hào)： TWL1110TQFP
廠商： Texas Instruments, Inc.
英文描述： VOICE-BAND AUDIO PROCESSOR VBAPE
中文描述： 語音頻帶音頻處理器VBAPE
文件頁數(shù)： 17/37頁
文件大?。?/td> 496K
代理商： TWL1110TQFP
TWL1110
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS103 – NOVEMBER 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
power supply rejection and crosstalk attenuation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage rejection, transmit channel
MIC1N, MIC1P =0 V,
VDD = 3 Vdc + 100 mVpeak to peak, f = 0 to 50 kHz
PCM code = positive zero,
VDD = 3 Vdc + 100 mVpeak to peak, f = 0 to 50 kHz
MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured
differentially between EAR1ON and EAR1OP
– 86
–70
dB
Supply voltage rejection, receive channel,
EAR1 selected (differential)
– 98
–70
dB
Crosstalk attenuation, transmit-to-receive
(differential)
70
dB
Crosstalk attenuation, receive-to-transmit
PCMIN = 0 dBm0, f = 300 to 3400 Hz measured at
PCMO, EAR1 amplifier
70
dB
switching characteristics
clock timing requirements for 2.048-MHz CLK
PARAMETER
MIN
NOM
MAX
UNIT
tt
f(mclk)
Transition time, MCLK
10
ns
MCLK frequency
2.048
MHz
MCLK jitter
37%
Number of PCMCLK clock cycles per PCMSYN frame
256
256
tc(PCMCLK)
PCMCLK clock period
156
488
512
ns
Duty cycle, PCMCLK
45%
50%
68%
transmit timing requirements for 2.048-MHz CLK (see Figure 8)
PARAMETER
MIN
20
MAX
UNIT
tsu(PCMSYN)
th(PCMSYN)
Setup time, PCMSYN high before falling edge of PCMCLK
tc(PCMCLK)–20
tc(PCMCLK)–20
ns
Hold time, PCMSYN high after falling edge of PCMCLK
20
receive timing requirements for 2.048-MHz CLK (see Figure 9)
PARAMETER
MIN
MAX
UNIT
tsu(PCSYN)
th(PCSYN)
tsu(PCMI)
th(PCMI)
Setup time, PCMSYN high before falling edge of PCMCLK
20
tc(PCMCLK)–20
tc(PCMCLK)–20
ns
Hold time, PCMSYN high after falling edge of PCMCLK
20
ns
Setup time, PCMI high or low before falling edge of PCMCLK
20
ns
Hold time, PCMI high or low after falling edge of PCMCLK
20
ns
clock timing requirements for 128-kHz CLK
PARAMETER
MIN
NOM
MAX
UNIT
tt
f(mclk)
Transition time, MCLK
10
ns
MCLK frequency
128
kHz
MCLK jitter
5%
Number of PCMCLK clock cycles per PCMSYN frame
16
16
tc(PCMCLK)
PCMCLK clock period
742.19
781.25
820.31
ns
Duty cycle, PCMCLK
40%
50%
60%
tc(PCMSYN)
PCMSYN clock period
125
μ
s
Duty cycle, PCMCLK
49.5%
50%
50.5%
相關(guān)PDF資料
PDF描述
TX45 HIGH-ENERGY TRIGGERED SPARK GAPS
XA1000 DC-18.0 GHz GaAs MMIC 5-Bit Digital Attenuator
XAUR13C 12.7mm (0.5 inch) 16 SEGMENT SINGLE DIGIT ALPHANUMERIC DISPLAY
XB1002 36.0-43.0 GHz GaAs MMIC Buffer Amplifier
XB1004 16.0-30.0 GHz GaAs MMIC Buffer Amplifier
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TWL1200 制造商:TI 制造商全稱:Texas Instruments 功能描述:SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER
TWL1200IPFBRQ1 功能描述:轉(zhuǎn)換 - 電壓電平 SDIO,UART,and Audio Vltg-Level Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
TWL1200-Q1 制造商:TI 制造商全稱:Texas Instruments 功能描述:SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER
TWL1200YFFR 功能描述:轉(zhuǎn)換 - 電壓電平 SDIO UART & Aud Vltg Level Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
TWL1200ZQCR 功能描述:轉(zhuǎn)換 - 電壓電平 SDIO UART & Audio Vltg-Level Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*