參數(shù)資料
型號(hào)： TTSI1K16T
英文描述： 1024-Channel, 16-Highway Time-Slot Interchanger
中文描述： 1024通道，16道時(shí)隙交換器
文件頁(yè)數(shù)： 59/64頁(yè)
文件大?。?/td> 1110K
代理商： TTSI1K16T
Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
59
Lucent Technologies Inc.
Timing Characteristics
(continued)
TDM highway timing is shown below for the following scenario (i = 0, 1, 2 . . . 15; j = 0, 1, 2 . . . 15):
I
The input CK speed is set to 8.192 MHz.
I
FSYNC is programmed to be active-high and sampled by a rising edge of CK.
I
The RXD[i] highway is set for 0-bit offset and a highway data rate of 4.096 Mbits/s.
I
The TXD[j] highway is set for 0-bit offset and a highway data rate of 8.192 Mbits/s.
5-7465(F)r.3
Figure 22. TDM Highway Timing
Table 50. TDM Highway Timing
The TDM highway timing numbers, t26—t30, also apply for all other cases as well, i.e.,
I
CK speed is 2.048 MHz, 4.096 MHz, or 16.384 MHz.
I
FSYNC is sampled on the falling edge of CK.
I
FSYNC is active-low.
I
RXD[i] is sampled on the falling edge of CK.
I
RXD[i] data rate is 2.048 Mbits/s or 8.192 Mbits/s.
I
TXD[j] is driven on the falling edge of CK.
I
TXD[j] data rate is 2.048 Mbits/s or 4.096 Mbits/s.
I
TXOE[j] is driven on the falling edge of CK. TXOE[j] is driven on the same edge as TXD[j].
Symbol
Description
Min
Max
Unit
t26
t27
t28
t29
t30
FSYNC, RXD[0—15] Setup to Active CK Edge
FSYNC, RXD[0—15] Hold from Active CK Edge
TXD[0—15] Delay from Active CK Edge (C
L
= 25 pF)
TXD[0—15] High Impedance (C
L
= 25 pF)
TXOE[0—15] Delay from Active CK Edge (C
L
= 20 pF)
10
5
5
—
5
—
—
15
15
15
ns
ns
ns
ns
ns
FSYNC
CK
RXD[i]
TXD[j]
FSYNC SAMPLED ACTIVE
TXOE[j]
t26
t27
t28
t29
BIT 0
t30
(8.192 MHz)
(4.096 Mbits/s)
t27
t26
BIT 1
BIT 2
BIT 5
BIT 6
BIT 5
t29
t30
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
(8.192 Mbits/s)
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