- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373747 > TTSI1K16T 1024-Channel, 16-Highway Time-Slot Interchanger PDF資料下載
參數(shù)資料
| 型號： | TTSI1K16T |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger |
| 中文描述： | 1024通道，16道時隙交換器 |
| 文件頁數(shù)： | 58/64頁 |
| 文件大?。?/td> | 1110K |
| 代理商： | TTSI1K16T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁當(dāng)前第58頁第59頁第60頁第61頁第62頁第63頁第64頁
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
58
Lucent Technologies Inc.
Timing Characteristics
(continued)
Table 49. Synchronous Microprocessor Interface Timing
* The CS setup timing requirement relative to PCLK can be programmed for either the first or second clock cycle of a microprocessor access
using CSV (bit 7) of the general command register.
The input setup timing requirement assumes a PCLK frequency of at least 25 MHz. For frequencies slower than 25 MHz, the D[7—0] propa-
gation delay must be less than 40 ns from the rising edge of PCLK which samples AS.
When data is driven by the TSI during a synchronous read cycle, good data is driven prior to DT being asserted.
Symbol
Description
Min
Max
Unit
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
CS Setup to Rising PCLK Edge
CS Hold from Rising PCLK Edge
AS Setup to Rising PCLK Edge
AS Hold from Rising PCLK Edge
R/W, A[14—0] Input Setup to Rising PCLK Edge
D[7—0] Input Setup to Rising PCLK Edge
R/W, A[14—0], D[7—0] Input Hold from Rising PCLK Edge
DT Output Delay from Rising PCLK Edge (C
L
= 10 pF to 50 pF)
DT High Impedance from Falling PCLK Edge (C
L
= 50 pF)
D[7—0] Output Delay from Rising PCLK Edge (C
L
= 50 pF)
D[7—0] Output High Impedance from Rising PCLK Edge
(C
L
= 10 pF to 50 pF)
10*
0
6
0
0
0
0
2.6
—
—
4
—
—
—
—
—
—
—
10
7
0
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TTSI1K16T3TL | 1024-Channel, 16-Highway Time-Slot Interchanger |
| TTSI1K16T | 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機(jī)) |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機(jī)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI1K16T3TL | 制造商:AGERE 制造商全稱:AGERE 功能描述:1024-Channel, 16-Highway Time-Slot Interchanger |
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。