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| 型號： | TTSI1K16T |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger |
| 中文描述： | 1024通道，16道時隙交換器 |
| 文件頁數(shù)： | 40/64頁 |
| 文件大?。?/td> | 1110K |
| 代理商： | TTSI1K16T |
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TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
40
Lucent Technologies Inc.
Configuration Register Architecture
(continued)
Table 23. Interrupt Mask Register (0x08)
Bit
7
6
Symbol
—
MASKFS
Name/Description
Reserved.
Read as 0.
Mask Frame Sync Error Interrupt.
Set this bit to a 1 to mask the generation of
an interrupt as a result of a frame sync error. Resets to a 1, which prevents the
status bit from generating an interrupt. Setting this bit to a 1 also prevents the
detection of a frame sync error and, thus, the setting of the FSERR bit in the
interrupt status register. This is done to prevent an unintended interrupt at the
first FSYNC pulse after the reset sequence.
Mask Test-Pattern Detection Interrupt.
Set this bit to a 1 to mask the genera-
tion of an interrupt as a result of a test-pattern detection. Resets to a 1, which
prevents the status bit from generating an interrupt.
Reserved.
Read as 1. Always write a 1 to this bit when writing this register.
Mask Error Detected Interrupt.
Set this bit to a 1 to mask the generation of an
interrupt as a result of a single bit error detected in the incoming test pattern.
Resets to a 1, which prevents the status bit from generating an interrupt.
Reserved.
Read as 1. Always write a 1 to this bit when writing this register.
Mask BIST Complete Interrupt.
Set this bit to a 1 to mask the generation of an
interrupt as a result of completing the memory BIST. Resets to a 1, which pre-
vents the status bit from generating an interrupt.
Mask Bit Errors Inserted Interrupt.
Set this bit to a 1 to mask the generation of
an interrupt as a result of completing the insertion of all requested bit errors.
Resets to a 1, which prevents the status bit from generating an interrupt.
5
MASKTPD
4
3
—
MASKERD
2
1
—
MASKBC
0
MASKBEI
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TTSI1K16T3TL | 1024-Channel, 16-Highway Time-Slot Interchanger |
| TTSI1K16T | 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機) |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI1K16T3TL | 制造商:AGERE 制造商全稱:AGERE 功能描述:1024-Channel, 16-Highway Time-Slot Interchanger |
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
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