參數(shù)資料
型號: TTRN012G5
英文描述: TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
中文描述: TTRN012G5(2.5 Gb /秒)和TTRN012G7(2.5 Gb /秒和2.7 Gb /秒)時鐘合成器,16:1數(shù)據(jù)復(fù)用器
文件頁數(shù): 19/22頁
文件大?。?/td> 394K
代理商: TTRN012G5
Preliminary Data Sheet
August 2000
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
19
Lucent Technologies Inc.
Timing Characteristics
Transmit Timing
Figure 8 shows the timing relationships between the 155.52 MHz or 166.62 MHz output clock (CK155P/N) and the
155.52 Mbits/s or 166.62 Mbits/s input data (D[15:0]P/N) and the input parity valid check (PARITYP/N). Also
shown is the relationship of the VALIDP/N output signal to CK155P/N; this relationship is true for both the contra-
clocking mode and the clockless transfer mode.
5-7726(F).hr.2
Note: T
SU
and T
HOLD
only apply in contra-clocking mode when CLKMODE = 1.
Figure 8. Transmit Timing Waveform
The 155 MHz or 166 MHz output clock and data signals from Figure 8 are characterized in Table 16.
Table 16. LVPECL Input/Output Pin ac Timing Characteristics
Applicable
Pins
CK155P/N
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Duty Cycle
155.52 MHz Clock Period
166.62 MHz Clock Period
All signals
differential
40
50
6.43
6.00
60
%
ns
ns
t
PERIOD
Input Timing
D[15:0]P/N,
PARITYP/N,
CK155P/N
t
SU
Setup from Clock Edge to
D[15:0]P/N or to
PARITYP/N Edge
Hold from Clock Edge to
D[15:0]P/N or to
PARITYP/N Edge
Rise, Fall Times:
20%—80%
Transition Skew Rise to Fall
CLKMODE = 1, All
signals differential
2.0
ns
t
HOLD
CLKMODE = 1,
All signals
differential
All signals
differential
0.5
ns
t
RISE
,
t
FALL
t
SKEW
200
500
800
ps
–100
0
100
ps
Output Timing
VALIDP/N,
CK155P/N
t
DD
Time Delay from Clock Edge
to VALIDP/N Edge
Rise, Fall Times:
20%—80%
Transition Skew Rise to Fall
All signals
differential
–300
800
1500
ps
t
RISE
,
t
FALL
t
SKEW
200
500
800
ps
–100
0
100
ps
OUTPUT
CK155P
CK155N
INPUTS
D[15:0]P/N,
PARITYP/N
t
SU
DATA 1
t
PERIOD
DATA 2
t
HOLD
OUTPUT
VALIDP/N
VALID 1
VALID 2
t
DD
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