參數(shù)資料
型號(hào)： TTRN012G5
英文描述： TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
中文描述： TTRN012G5（2.5 Gb /秒）和TTRN012G7（2.5 Gb /秒和2.7 Gb /秒）時(shí)鐘合成器，16:1數(shù)據(jù)復(fù)用器
文件頁(yè)數(shù)： 11/22頁(yè)
文件大?。?/td> 394K
代理商： TTRN012G5
Preliminary Data Sheet
August 2000
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
11
Lucent Technologies Inc.
Functional Overview
(continued)
Multiplexer Operation
The parallel 155 Mbits/s data is clocked into an input buffer by a 155 MHz clock derived from the synthesized
2.5 GHz clock. The data is checked for parity and then clocked into a 16:1 multiplexer. The relationship between
the parallel D[15:0] input data and the serial output data (D2G5P/N) is given in Figure 5. The D15 bit is the most
significant bit (MSB) and is shifted out first in time in the serial output stream.
5-8063(F)
Figure 5. Parallel Input to Serial Output Data Relationship
High-Speed Serial Clock Output Enable (ENCK2G5)
A separate output enable is provided for the 2.5 GHz clock output (CK2G5P/N). The enable is an active-high
CMOS input with an internal pull-up resistor. The default condition will enable the CK2G5P/N output, and applying
a ground or setting the enable pin (ENCK2G5) to logic low will disable the CK2G5P/N output. When disabled, the
CK2G5P/N output pins should be either left floating, or be connected to a load which returns to V
CC
. The output
must not be connected directly to ground when it is disabled.
Loopback 2.5 GHz Data Output (LBDP/N, ENLBDN)
An alternate 2.5 Gbits/s CML data output is available on the LBDP/N pin. This pin is provided for use in system
loopback testing and avoids the need for off-chip signal splitting of the data signal path. The alternate
2.5 Gbits/s loopback data output may be enabled by setting the ENLBDN pin to logic low. ENLBDN enable is an
active-low CMOS input with an internal pull-up resistor so the default condition will disable the LBDP/N output, and
a ground or logic-low signal must be applied to enable the loopback output. When disabled, the LBDP/N pin should
be either left floating, or be connected to a load which returns to V
CC
. The output must not be connected directly to
ground when it is disabled.
Parity Validation (VALIDP/N)
The parity signal is expected to be a logic 0 when the number of 1s in the 16-bit input register is an even number,
and the parity signal is expected to be a logic 1 when the number of 1s in the input register is an odd number. If the
parity bit agrees with the parity in the input register, then the VALIDP/N signal will be logic high. If the parity signal
is not generated, the VALIDP/N pin should be left open without termination to avoid meaningless signal swings and
avoid unnecessary power dissipation.
D15
(MSB)
D14
D1
D0
D15
TIME
(D15 SERIALLY SHIFTED OUT FIRST)
(D0 SERIALLY SHIFTED OUT LAST)
(LSB)
相關(guān)PDF資料
PDF描述
TTRN012G7 TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G5 Clock Synthesizer, 16:1 Data Multiplexer(2.5 Gbits/s)(時(shí)鐘合成器，16：1數(shù)據(jù)多路復(fù)用器(2.5 G位/秒))
TTRN012G7 Clock Synthesizer, 16:1 Data Multiplexer(2.5 Gbits/s and 2.7 Gbits/s)(時(shí)鐘合成器，16：1數(shù)據(jù)多路復(fù)用器(2.5 G位/秒和2.7 G位/秒）)
TTS3816B4E 2M x 16Bit x 4 Banks synchronous DRAM
TTS3816B4E-6 2M x 16Bit x 4 Banks synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TTRN012G53XE1 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G7 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G73XE1 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
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