參數(shù)資料
型號(hào)： TTRN012G5
英文描述： TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
中文描述： TTRN012G5（2.5 Gb /秒）和TTRN012G7（2.5 Gb /秒和2.7 Gb /秒）時(shí)鐘合成器，16:1數(shù)據(jù)復(fù)用器
文件頁(yè)數(shù)： 12/22頁(yè)
文件大?。?/td> 394K
代理商： TTRN012G5
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
Preliminary Data Sheet
August 2000
12
Lucent Technologies Inc.
Clocking Modes and Timing Adjustments
Clockless Transfer Mode
(CLKMODE, EXTADJN, MONAPAP/N)
The device supports two timing modes for the 155 Mbits/s data input. In clockless transfer mode (CLKMODE = 0),
data may be sent to the device without a clock. After phase/frequency lock has been obtained by the clock
synthesizer, the device automatically finds the correct phase of the internal 155 MHz clock by sampling the rising
edge of the D0P/N data bit. The skew of any data bit D[15:0]P/N must be less than 500 ps relative to D0P/N. If the
phase of the incoming data shifts more than ±2400 ps from the time the automatic phase adjustment occurred, the
device will automatically readjust its internal clocking phase. Data integrity may not be obtained at the instant of
phase adjustment, and an error burst of up to 16 data bits may occur.
The user may optionally force the automatic phase adjustment to occur by toggling the EXTADJN pin (active-low)
and keeping it low for at least 12.8 ns after the next rising edge of the D0P/N input. The phase will be adjusted one
time upon the first occurrence of a low-to-high transition of the D0P/N data bit while the EXTADJN pin is in the
logic-low state. To externally adjust the phase again, the RESETN pin must be brought low then high to enable
another phase adjustment. When CLKMODE = 0, the 155 MHz output clock (CK155P/N) is active but should be
left unconnected to conserve power.
MONAPAP/N can be used for the monitoring and reporting of phase adjustments. The MONAPAP/N output will go
high in the following sequence:
I
EXTADJN pin transitions to logic-low state
I
A rising edge of the D0P/N input occurs
I
MONAPAP/N transitions to logic 1 three CK2G5 cycles (1.2 ns) later
I
MONAPAP/N will stay high for 12 CK2G5 cycles (4.8 ns)
The first sixteen D2G5 data output bits after the rising edge of MONAPAP/N are invalid.
相關(guān)PDF資料
PDF描述
TTRN012G7 TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G5 Clock Synthesizer, 16:1 Data Multiplexer(2.5 Gbits/s)(時(shí)鐘合成器，16：1數(shù)據(jù)多路復(fù)用器(2.5 G位/秒))
TTRN012G7 Clock Synthesizer, 16:1 Data Multiplexer(2.5 Gbits/s and 2.7 Gbits/s)(時(shí)鐘合成器，16：1數(shù)據(jù)多路復(fù)用器(2.5 G位/秒和2.7 G位/秒）)
TTS3816B4E 2M x 16Bit x 4 Banks synchronous DRAM
TTS3816B4E-6 2M x 16Bit x 4 Banks synchronous DRAM
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TTRN012G53XE1 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G7 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G73XE1 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTR-RED 功能描述:打印機(jī) Ribbon, Resin, 4.33" W x 299’ L, for use RoHS:否 制造商:Seiko Instruments 產(chǎn)品:Printer 電源電壓: 每行點(diǎn)數(shù):9 x 320 打印速度:52.5 cps, 80 cps 紙張寬度:112 mm
TTRW2-BL 功能描述:打印機(jī) Ribbon, Wax, 2.50" W x 280’ L, for use w RoHS:否 制造商:Seiko Instruments 產(chǎn)品:Printer 電源電壓: 每行點(diǎn)數(shù):9 x 320 打印速度:52.5 cps, 80 cps 紙張寬度:112 mm
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