參數(shù)資料
型號(hào): TSS463-AAR
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: VAN Data Link Controller with Serial Interface
中文描述: 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDSO16
封裝: SOP-16
文件頁(yè)數(shù): 8/60頁(yè)
文件大?。?/td> 816K
代理商: TSS463-AAR
8
TSS463-AA
4205B–AUTO–12/04
When the master (CPU) conducts a read, it sends an address byte, a control byte and
dummy characters ("0xFF" for instance) on its MOSI line. In the case of a VAN mes-
sages RAM read (VAN frame received), the first data byte sent back by the TSS463AA
on its MISO pin is the
data length
so the master knows how many dummy characters it
must send to read the VAN frame properly. When the TSS463AA responds back with
data, it will not take care of the MOSI line.
The master must activate and de-activate SS between each data frame.
Synchronization bytes must be monitored carefully. For instance, if “0xAA” and “0x55”
are not monitored correctly, then the previous transmission may be incorrect too.
A control byte containing "0x00" or "0xFF" is forbidden except during an "Initialization
Sequence".
Intel SPI Mode
The Intel SPI mode is the second type of interface. As mentioned before, the TSS463AA
enters this mode if the Initialization Sequence contains (first two bytes received) "0xFF,
0xFF".
This mode is fully compatible to the Intel UART serial interface programmed in mode 0
only. It is the same as Motorola SPI mode (same CPOL and CPHA) but with inverted
communication sense (LSB first and MSB last). The protocol is also the same.
However, from the master point of view (host microcontroller), the hardware is different.
Figure 5 shows how to connect the TSS463AA and Intel type microcontroller.
Figure 5.
Typical Application With the 8051 UART in Mode 0
Notes:
1. The RESET pin can either be connected to GND through a 1 μF capacitor, or the
microcontroller RESET pin or unconnected (inactive with internal pull-up).
INT
IRQ
PORT X.z
SS
PORT X.y
RXD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
MISO
MOSI
RxD0
RxD1
RxD2
TXD
RESET (1)
VDD
GND
CKOUT
XTAL1
XTAL2
TXD
VAN Bus
General I/O
Remaining pins
TEST/VSS
XTAL1
C1
C2
100k
(if needed)
optional
RESET (1)
16
M
T
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