參數(shù)資料
型號(hào)： TSS463-AAR
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： VAN Data Link Controller with Serial Interface
中文描述： 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDSO16
封裝： SOP-16
文件頁(yè)數(shù)： 18/60頁(yè)
文件大?。?/td> 816K
代理商： TSS463-AAR
18
TSS463-AA
4205B–AUTO–12/04
However, since the CRC is calculated automatically from the identifier, command and
data fields by the TSS463AA, therefore, the user should not be concerned with the cir-
cuit. When the frame check sequence has been transmitted, the transmitting module
must transmit an End of Data (EOD) sequence, followed by the ACKnowledge field
(ACK) and the End of Frame sequence (EOF) to terminate the transfer.
Figure 16.
Acknowledge Sequences
Frame Examples
The frames transmitted on the VAN bus are generated by several modules, each sup-
plying different parts of the message. Figure 17 through Figure 20 show the four frame
types specified in the VAN standard, and the module that is generating the different
fields.
The most straightforward frame is the normal data frame in Figure 17. Like all other
frames, it is initiated with a SOF sequence. This sequence is generated by a bus
master (not shown in the figure).
During this frame, there is basically only one module transmitting with the exception of
the acknowledgement, generated by the receiving module if requested in the RAK bit.
The reply request frame with immediate reply in Figure 18 is the only frame in which
a slave module can transmit data by filling it into the appropriate field.
The only difference for the frame on the bus is that the R/W bit has changed state com-
pared to the normal frame.
This is a highly interactive frame where a bus master generates the SOF and the initia-
tor generates the identifier, the three first bits of the command, and the acknowledge.
The RTR bit, the data field, the frame check, the EOD and the EOF are all generated by
the replying module.
The reply request frame with deferred reply in Figure 19 is basically the same frame
as the reply request frame with immediate reply, but since the requested module
does not generate the RTR bit the requesting module will continue with the frame
check, the EOD and the EOF.
During this frame, the requested module will only generate the acknowledge, and only if
this was requested by the initiator through the RAK bit.
Finally, the deferred reply frame in Figure 20 which is sent when a module has
prepared a reply for a reply request that has been received earlier.
This frame very closely mimics the normal data frame with the exception is the R/W bit
that has changed state.
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
POSITIVE ACKNOWLEDGE
ABSENT ACKNOWLEDGE
0
8
16
24
32
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSS463A-TERZ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC ASICS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
TSS463B 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Serial VAN Data Link Controller
TSS463B_03 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Serial VAN Data Link Controller
TSS463B_04 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller with Serial Interface
TSS463B-TERA 制造商:Temic 功能描述:LAN Node Controller, 16 Pin, SOP
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