參數(shù)資料
型號: TSS461E-TRDZ-9
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: VAN Data Link Controller
中文描述: 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDSO24
封裝: SO-24
文件頁數(shù): 15/57頁
文件大?。?/td> 817K
代理商: TSS461E-TRDZ-9
15
TSS461E
4194B–AUTO–12/04
After the command field comes the data field. This is just a sequence of bytes transmit-
ted, MSB first. In the VAN standard the maximum message length is set to 28 bytes, but
the TSS461E handles messages up to 30 bytes.
The next field is the FCS field. This field is a 15 bit CRC checksum defined by the follow-
ing generator polynomial g(x) of order 15:
g(x) = x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1
The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is
performed before transmission.
However, since the CRC is calculated automatically from the identifier, command and
data fields by the TSS461E, the user should not be concerned with the circuit. When the
frame check sequence has been transmitted, the transmitting module must transmit an
End Of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of
Frame sequence (EOF) to terminate the transfer.
Figure 11.
Acknowledge Sequences
Frame Examples
The frames transmitted on the VAN bus are generated by several modules, each sup-
plying different parts of the message. Figure 12 through Figure 15 show the four frame
types specified in the VAN standard, and what module is generating the different fields.
The most straightforward frame is the normal data frame in Figure 13. Like all other
frames it is initiated with a SOF sequence. This sequence is generated by a bus
master (not shown in figure).
During this frame, there is basically only one module transmitting with the exception
being the acknowledgement, generated by the receiving module if requested in the
RAK bit.
The reply request frame with immediate reply in Figure 13 is the only frame in which
a slave module can transmit data by filling it into the appropriate field.
The difference for the frame on the bus is that the R/W bit has changed state
compared to the normal frame.
This is a highly interactive frame where a bus master generates the SOF and the
initiator generates the identifier, the three first bits of the command, and the
acknowledge. The RTR bit, the data field, the frame check, the EOD and the EOF
are all generated by the replying module.
The reply request frame with deferred reply in Figure 14 is the same frame as the
reply request frame with immediate reply. But since the requested module does not
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
POSITIVE ACKNOWLEDGE
ABSENT ACKNOWLEDGE
0
8
16
24
32
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參數(shù)描述
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