參數(shù)資料
型號: TSS461E-TRDZ-9
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: VAN Data Link Controller
中文描述: 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDSO24
封裝: SO-24
文件頁數(shù): 12/57頁
文件大小: 817K
代理商: TSS461E-TRDZ-9
12
TSS461E
4194B–AUTO–12/04
Figure 6.
State Encoding
In Figure 6 the pulsed waveforms are shown. In Figure 9 through Figure 15 the low
"timeslots" (i.e. blocks of 16 prescaled clocks) should be replaced by the dominant
waveform showed in Figure 6, if the correct representations for pulsed coding is desired.
VAN Frame
Figure 7.
VAN Bus Frame
The VAN bus supports three different module (unit) types:
1.
The Autonomous module, which is a bus master. It can transmit Start Of Frame
(SOF) sequences, it can initiate data transfers and can receive messages.
2.
The Synchronous access module. It cannot transmit SOF sequences, but it can
initiate data transfers and can receive messages.
3.
The Slave module, which can only transmit using an in-frame mechanism and
can receive messages.
Figure 8.
Hierarchical Access Methods
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
NORMAL OR PULSED RECESSIVE STATE
NORMAL DOMINANT STATE
PUSED DOMINANT STATE
0
4
8
12
16
2
6
10
14
SOF
Identifier
Field
Command
Data
Field
Frame
Check
Sum
EOD
ACK
EOF
EXT
RAK
R/W
RTR
SOF
ID
COM
DATA
ACK
EOF
EOD
Autonomous
Rank 0
ID
COM
DATA
FCS
ACK
EOF
EOD
Synchronous
Rank 1
DATA
FCS
ACK
EOF
EOD
Slave
Rank 16
R
FCS
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