參數(shù)資料
型號: TSS461CR
英文描述: LAN Node Controller
中文描述: 網(wǎng)絡(luò)節(jié)點(diǎn)控制器
文件頁數(shù): 6/52頁
文件大?。?/td> 268K
代理商: TSS461CR
TSS461C
6
Rev. D (22 Feb 01)
5.2. Interrupts
If an event occurs in the TSS461C, that needs the attention of the processor, this will be signalled on the active low,
open drain interrupt request pin. Which events that create such a request is controlled by the internal registers.
Every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0B) the INT pin will be
released momentarily. This enables the TSS461C to work with processors that have either edge or level sensitive
interrupt inputs.
5.3. Reset
The reset is applied asynchronously regarding XTAL clock. It can be done either by the RESET pin or by software.
The RESET pin is a CMOS trigger input with a pull-down resistor (
provides to RESET pin an efficient behavior.
The software reset is made through the GRES command bit of the Command Register (0x03).
The two resets are ored, filtered and gauging. Then the internal reset, always asserted asynchronously, enables the
internal oscillator. Then it waits for eight clock periods the oscillator stability.
The different blocks of the TSS461C need to be turned on synchronously. So the release of the internal reset is
synchronous and a loose of clock can let the TSS461C in permanent reset after applying Reset.
110k ). An external 1 F capacitor to Vcc
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