參數(shù)資料
型號(hào)： TSPC860XRMZPU66D
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁(yè)數(shù)： 71/93頁(yè)
文件大?。?/td> 1601K
代理商： TSPC860XRMZPU66D
71
TSPC860 [Preliminary]
2129B–HIREL–12/04
SCC In NMSI Mode
Electrical Specifications
Table 20.
NMSI External Clock Timing
Notes:
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1.
2. Also applies to CD and CTS hold time when they are used as an external sync signals.
Notes:
1. The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1
2. Also applies to CD and CTS hold time when they are used as an external sync signals.
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLK1 and TCLK1 Width High
(1)
1/SYNCCLK
–
ns
101
RCLK1 and TCLK1 Width Low
1/SYNCCLK + 5
–
ns
102
RCLK1 and TCLK1 Rise/Fall Time
–
15
ns
103
TXD1 Active Delay (From TCLK1 Falling Edge)
0
50
ns
104
RTS1 Active/Inactive Delay (From TCLK1 Falling Edge)
0
50
ns
105
CTS1 Setup Time to TCLK1 Rising Edge
5
–
ns
106
RXD1 Setup Time to RCLK1 Rising Edge
5
–
ns
107
RXD1 Hold Time from RCLK1 Rising Edge
(2)
5
–
ns
108
CD1 Setup Time to RCLK1 Rising Edge
5
–
ns
Table 21.
NMSI Internal Clock Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLK1 and TCLK frequency1
(1)
0
SYNCCLK/3
MHz
102
RCLK1 and TCLK1 Rise/Fall Time
–
–
ns
103
TXD1 Active Delay (From TCLK1 Falling Edge)
0
30
ns
104
RTS1 Active/Inactive Delay (From TCLK1 Falling Edge)
0
30
ns
105
CTS1 Setup Time to TCLK1 Rising Edge
40
–
ns
106
RXD1 Setup Time to RCLK1 Rising Edge
40
–
ns
107
RXD1 Hold Time from RCLK1 Rising Edge
(2)
0
–
ns
108
CD1 Setup Time to RCLK1 Rising Edge
40
–
ns
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