- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373744 > TSPC860XRMZPU66D (Atmel Corp.) Integrated Communication Processor PDF資料下載
參數(shù)資料
| 型號： | TSPC860XRMZPU66D |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Communication Processor |
| 中文描述： | 綜合通信處理器 |
| 文件頁數(shù)： | 12/93頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | TSPC860XRMZPU66D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
12
TSPC860 [Preliminary]
2129B–HIREL–12/04
BG
Hi-Z
E2
Bidirectional
Bus Grant—Asserted low when the arbiter of the external bus grants
the bus to a specific device. When the TSPC860 is configured to
work with the internal arbiter, BG is configured as an output and
asserted every time the external master asserts BR and its priority
request is higher than any internal sources requiring a bus transfer.
However, when the TSPC860 is configured to work with an external
arbiter, BG is an input.
BB
Hi-Z
E1
Bidirectional
Active Pull-up
Bus Busy—Asserted low by a master to show that it owns the bus.
The TSPC860 asserts BB after the arbiter grants it bus ownership
and BB is negated.
FRZ
IRQ6
See Section
“Signal
States During
Hardware
Reset” on
page 27
G3
Bidirectional
Freeze—Output asserted to indicate that the core is in debug mode.
Interrupt Request 6—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of FRZ/IRQ6 (if defined as IRQ6) and
DP3/IRQ6 (if defined as IRQ6).
IRQ0
Hi-Z
V14
Input
Interrupt Request 0—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
IRQ1
Hi-Z
U14
Input
Interrupt Request 1—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
IRQ7
Hi-Z
W15
Input
Interrupt Request 7—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
CS(0-5)
High
C3, A2,
D4, E4,
A4, B4
Output
Chip Select—These outputs enable peripheral or memory devices at
programmed addresses if they are appropriately defined. CS0 can
be configured to be the global chip-select for the boot device.
CS6
CE1_B
High
D5
Output
Chip Select 6—This output enables a peripheral or memory device
at a programmed address if defined appropriately in the BR6 and
OR6 in the memory controller.
Card Enable 1 Slot B—This output enables even byte transfers when
accesses to the PCMCIA Slot B are handled under the control of the
PCMCIA interface.
CS7
CE2_B
High
C4
Output
Chip Select 7—This output enables a peripheral or memory device
at a programmed address if defined appropriately in the BR7 and
OR7 in the memory controller.
Card Enable 2 Slot B—This output enables odd byte transfers when
accesses to the PCMCIA Slot B are handled under the control of the
PCMCIA interface.
Table 1.
Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSPC860XRMZQU66D | Integrated Communication Processor |
| TSPC860XRVZPU66D | Integrated Communication Processor |
| TSPC860XRVZQU66D | Integrated Communication Processor |
| TSS10G45S | SOLID STATE AC RELAY |
| TSS10J45S | SOLID STATE AC RELAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSPC860XRMZQU66D | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Communication Processor |
| TSPC860XRVZPU66D | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Communication Processor |
| TSPC860XRVZQU66D | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Communication Processor |
| TSPC-DCM600 | 制造商:Traco Power 功能描述:Bulk |
| TSPCOS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TREND SERVER PROG MULTI |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。