參數(shù)資料
型號(hào)： TSL2569T
廠商： AMS-TAOS USA Inc
文件頁(yè)數(shù)： 14/37頁(yè)
文件大?。?/td> 785K
描述： IC LIGHT TO DGTL CONV 6-TMB
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： TSL2569-TDKR
TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D  DECEMBER 2008
13
The LUMENOLOGY r Company
r
r
Copyright E 2008, TAOS Inc.
www.taosinc.com
Timing Register (1h)
The TIMING register controls both the integration time and the gain of the ADC channels. A common set of
control bits is provided that controls both ADC channels. The TIMING register defaults to 02h at power on.
Table 5. Timing Register
6
7
5
4
INTEG
2
3
1
0
0
0
0
0
0
0
1
0
Reset Value:
TIMING
Manual
Resv
Resv
GAIN
Resv
Resv
1h
FIELD
BIT
DESCRIPTION
Resv
75
Reserved. Write as 0.
GAIN
4
Switches gain between low gain and high gain modes. Writing a 0 selects low gain (1?/SPAN>); writing a 1 selects
high gain (16?/SPAN>).
Manual
3
Manual timing control. Writing a 1 begins an integration cycle. Writing a 0 stops an integration cycle.
NOTE:  This field only has meaning when INTEG = 11.  It is ignored at all other times.
Resv
2
Reserved. Write as 0.
INTEG
1:0
Integrate time. This field selects the integration time for each conversion.
Integration time is dependent on the INTEG FIELD VALUE and the internal clock frequency. Nominal integration
times and respective scaling between integration times scale proportionally as shown in Table 6. See Note 5
and Note 6 on page 5 for detailed information regarding how the scale values were obtained; see page 22 for
further information on how to calculate lux.
Table 6. Integration Time
INTEG FIELD VALUE
SCALE
NOMINAL INTEGRATION TIME
00
0.034
13.7 ms
01
0.252
101 ms
10
1
402 ms
11

N/A
The manual timing control feature is used to manually start and stop the integration time period. If a particular
integration time period is required that is not listed in Table 6, then this feature can be used. For example, the
manual timing control can be used to synchronize the TSL256x device with an external light source (e.g. LED).
A start command to begin integration can be initiated by writing a 1 to this bit field. Correspondingly, the
integration can be stopped by simply writing a 0 to the same bit field.
Interrupt Threshold Register (2h  5h)
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison
function for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low
threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses
above the high threshold specified, an interrupt is asserted on the interrupt pin. Registers THRESHLOWLOW
and THRESHLOWHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold.
Registers THRESHHIGHLOW and THRESHHIGHHIGH provide the low and high bytes, respectively, of the
upper interrupt threshold. The high and low bytes from each set of registers are combined to form a 16-bit
threshold value. The interrupt threshold registers default to 00h on power up.
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