參數(shù)資料
型號: TSC2300IPAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 70/83頁
文件大小: 1268K
代理商: TSC2300IPAGRG4
www.ti.com
TSC2300
SLAS372 — NOVEMBER 2002
KCLN[3:0] = 0001 = 4 periods of the keyclick sound (default)
KCLN[3:0] = 0010 = 6 periods of the keyclick sound
KCLN[3:0] = 0011 = 8 periods of the keyclick sound
KCLN[3:0] = 1111 = 32 periods of the keyclick sound (max)
Bit 3 RESERVED
This bit is reserved, and should be written as 0. If read, it is read back as 0.
Bit 2 MONS
Mono Select. This bit determines the position of the Mono multiplexer. This multiplexer allows either the audio ADC
Input or the mono mix of the stereo line outputs to be played out the differential mono output (MONO+/-).
Table 40. Mono Select
MONS
DESCRIPTION
0
Mono output comes from ADC input (default)
1
Mono output comes from mono mix of line outputs
Bit 1 SSRTE
Volume Soft-stepping Rate Select. This bit selects the speed of the soft-stepping function of the TSC2300 volume
controls. At normal speed, the actual volume is updated approximately once every 20 s. At half speed, the actual
volume is updated approximately once every 40 s.
Table 41. Volume Soft-Stepping Rate Select
SSRTE
DESCRIPTION
0
Normal step rate used (default)
1
Half step rate used
Bit 0 SSTEP
Soft-step Flag. This read-only bit indicates that the TSC2300 volume control soft-stepping is completed.
Table 42. Soft-Step Flag
SSTEP
DESCRIPTION
0
Soft-stepping is not complete
1
Soft-stepping is complete (default)
AUDIO POWER CONTROL REGISTER (Page 2, Address 05H)
The audio power / miscellaneous control register of the TSC2300 controls the powering down of various audio blocks
of the TSC2300. The default state of the TSC2300 has all audio blocks powered down. Before using any of the audio
blocks, they must be powered up by writing to this register. This register also controls the crystal oscillator clock and
buffer, the bass-boost filter, and the de-emphasis filter.
The audio power / miscellaneous control register is formatted as follows:
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 LSB
MSB
APD
AVPD
ABPD
HAPD
MOPD
DAPD
ADPDL
RESV
PDSTS
MIBPD
OSCC
BCKC
SMPD
OTSYN
BASS
DEEMP
For bits 15 through 8 of this register, writing a 1 to a selected bit powers down the affected section, writing a 0 powers
up the section.
Bit 15 APD
72
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