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參數(shù)資料
| 型號： | TSC2300IPAGRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 61/83頁 |
| 文件大?。?/td> | 1268K |
| 代理商： | TSC2300IPAGRG4 |
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Default Bass-Boost Transfer Function 48 kHz Mode
1
10
100
1000
10000
100000
Frequency (Hz)
0
–0.5
–1
–1.5
–2
–2.5
–3
–3.5
Gain
(dB)
TSC2300
SLAS372 — NOVEMBER 2002
Figure 77. Transfer Function of Default Bass-Boost Filter Coefficients at 48-kHz Sampling Rate.
Audio ADC
The audio ADC consists of a 4th order multi-bit analog delta-sigma modulator, followed by a digital decimation filter.
The digital output data is then passed to the bus interface for transmission back to the CPU.
The analog modulator is a fully differential switched-capacitor design with multi-bit quantizer and dynamic element
matching to avoid mismatch errors. The modulator operates at an oversampling ratio of 128 for all sample rates. The
input to the ADC is filtered by a single-pole analog filter with -3-dB point at approximately 500 kHz for antialiasing. This
analog filter uses a single off-chip 1 nF cap per ADC (at the AFILT pins) and on-chip resistor.
The digital decimation filter block includes a high-pass IIR filter for the purpose of removing any dc or
sub-audio-frequency component from the signal. Since such a low frequency filter can have significant settling time, the
filter has an adjustable cutoff frequency, in order to allow the host to set a faster settling time initially, then later switch
it back to a level that does not affect the audio band. The settings for this high-pass filter are:
HPF -3-dB frequency:
0.000019 Fs (0.912 Hz at Fs=48 kHz)
0.000078 Fs (3.744 Hz at Fs=48 kHz)
0.1 Fs (4.8 kHz at Fs=48 kHz)
The filter block provides an audio passband ripple of +/-0.03 dB over a passband from 0 Hz to 0.454 Fs, and 70-dB
minimum stopband attenuation from 0.548 Fs to 64 Fs.
The ADC modulator and digital filter operate on a clock that changes directly with sampling frequency (Fs). This is in
contrast to the DAC, which keeps the modulator running at a high rate of 128 x 44.1 kHz or 128 x 48 kHz even if the
incoming data rate is much lower, such as 8 kHz. Group delay of the ADC path varies with sampling frequency and is
given by 28.7/Fs.
Audio ADC SNR performance is 88-dB-A typical over 20-Hz - 20-kHz bandwidth in 44.1/48-kHz mode with a 3.3-V
supply level.
The audio ADC is preceded by an analog volume control with gain programmable from 20 dB to -40 dB or mute in
0.5-dB steps using Reg 01h, Pg 2. The input to the volume control is selected as LLINEIN, RLINEIN, MICIN, or a mono
mix of LLINEIN and RLINEIN through the INM bits (Bits [13:12], Reg 00h, Pg 2). An additional preamp gain is
selectable on the MICIN input as 0 dB, 6 dB, or 12 dB using the MICG bits (Bits [9:8], Reg 00h, Pg 2).
64
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| TSC2301IGQZR | 功能描述:觸摸屏轉(zhuǎn)換器和控制器 Prog 4-Wire w/20-Bit Stereo Audio Codec RoHS:否 制造商:Microchip Technology 類型:Resistive Touch Controllers 輸入類型:3 Key 數(shù)據(jù)速率:140 SPS 分辨率:10 bit 接口類型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 電源電壓:2.5 V to 5.25 V 電源電流:17 mA 工作溫度:- 40 C to + 85 C 封裝 / 箱體:SSOP-20 |
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