參數(shù)資料
型號: TSC2300IPAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 55/83頁
文件大?。?/td> 1268K
代理商: TSC2300IPAGRG4
www.ti.com
TSC2300
SLAS372 — NOVEMBER 2002
The common-mode voltage, VCM, used by the audio section can be powered up independently by the AVPD bit (Bit
14, Reg 05h, Pg 2). Because the audio outputs are biased to this voltage, this voltage is slowly ramped up when
powered on, and there is an internally programmed delay of approximately 500 msec between powering up this voltage
and unmuting the analog audio signals of the TSC2300, in order to avoid pops and clicks on the outputs. It is
recommended to keep VCM powered up if the 500-msec delay is not tolerable.
Audio Digital I/O
Digital audio data samples can be transmitted between the TSC2300 and the CPU via the I2S bus (BCLK, LRCLK,
I2SDIN, I2SDOUT). However, all registers, including those pertaining to audio functionality, are only accessible via the
SPI bus. The I2S bus operates only in slave mode, meaning the BCLK and LRCLK must be provided as inputs to the
part. Four programmable modes for this serial bus are supported and can be set through the I2SFM bits (Bits[1:0], Reg
00h, Pg 2) .
PCM Audio Interface
The 4-wire digital audio interface for TSC2300 is comprised of BCLK (pin 24), LRCLK (pin 25), I2SDIN (pin 26), and
I2SDOUT (pin 27). For the TSC2300, these formats are selected through the I2SFM bits in Reg 00h, Pg 2. The
following figures illustrate audio data input/output formats and timing.
The TSC2300 can accept 32-, 48- or 64-bit clocks (BCKIN) in one clock of LRCIN. Only 16-bit data formats can be
selected when 32-bit clocks/LRCIN are applied.
59
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