參數資料
型號: TS86101G2BCGL
廠商: E2V TECHNOLOGIES PLC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
封裝: HERMETIC SEALED, CERAMIC, BGA-255
文件頁數: 56/57頁
文件大?。?/td> 1030K
代理商: TS86101G2BCGL
8
0992D–BDC–04/09
TS86101G2B
e2v semiconductors SAS 2009
2.2
Timing Characteristics
Notes:
1. Digital input data rise/fall time: defined between 20% to 80%.
2. Exclusive of period (pp) jitter on both Data and on Data Ready.
3. CW_IN clock input jitter over 5 GHz bandwidth. MUXDAC also operates with CW_IN clock showing more jitter but this may
degrade performance (SNR and NPR).
4. Guaranteed by design.
6. TPD can be directly measured at package input/output, between CW_IN clock and analog output.
7. Full-scale analog output (10% to 90%).
Table 2-4.
Timing Characteristics: 50
Ω // 2pF Loading Conditions on Each Single-ended Output. Absolute Timing
Values are Given at Package Input/Output Balls
Parameter
Test
Level
Min
Typ
Max
Data and data ready maximum allowable input jitter
4
300 ps peak- to-
peak
Input data rise/fall time(1)
Data ready rise/fall time(1)
4
500 ps
4
–1.3 ns
2.5 ns
Input data rate (ports A, B, C and D)
4
350 MWords/s
Input data pulse width (ports A, B, C and D)
4
5.7 ns
(at 350 MWord/s)
CW_IN clock input frequency
4
1400 MHz
CW_IN master clock input jitter
41 ps rms
CW_IN to DSP clock output delay with clock shift 0000
CW_IN to DSP clock output delay with clock shift 1111
DSP clock output phase tuning range
DSP clock output phase tuning steps
4
1
2.1 ns + 1 clock cycle
5.2 ns + 1 clock cycle
0 to 3.1 ns
200 ps
Data ready to CW_IN clock timing: (Figure 5-4 on page 22)
Forbidden area
4
600 ps
Pipeline delay(4)
TOD(5)
TPD(5)(6) (propagation delay)
Analog output rise/fall time(7)
4
1 clock cycle
3.7 ns
Pipeline delay + TOD
180 ps
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