參數(shù)資料
型號(hào)： TS86101G2BCGL
廠商： E2V TECHNOLOGIES PLC
元件分類： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
封裝： HERMETIC SEALED, CERAMIC, BGA-255
文件頁數(shù)： 37/57頁
文件大?。?/td> 1030K
代理商： TS86101G2BCGL
42
0992D–BDC–04/09
TS86101G2B
e2v semiconductors SAS 2009
Figure 12-10. DSP Output Clock Implementation (General Case – Values Given For Information Only)
Notes:
1. The 100
Ω differential resistor is required for impedance matching of the output buffer of the MUXDAC. It
must be placed right after the MUXDAC buffer and not at the end of the line (i.e. close to the load)
because of the biasing resistors used after the AC coupling capacitors (it would change the biasing).
2. The 100
Ω differential resistor, the AC coupling capacitors and the resistors used for the biasing should
all be placed as close as possible to the load.
3. Even without 100
Ω differential resistor, the impedance of the output buffer is sufficient. In that case the
swing of DSP output clock is twice larger and common mode remains unchanged.
VCCD
DGND
10 nF
DSP_CK_T
DSP_CK_F
50
Ω
50
Ω Lines
High Impedence
Load
100
Ω
1 K
Ω
10 nF
GND
1.5V
3.3V
100 K
Ω
As close as possible to the load
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