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參數(shù)資料
| 型號(hào)： | TS68C429AVR |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT |
| 中文描述： | 3 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數(shù)： | 25/43頁 |
| 文件大?。?/td> | 1638K |
| 代理商： | TS68C429AVR |
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25
TS68C429A
2120A–HIREL–08/02
Microprocessor Interface Unit
(MIU)
This interface which is directly compatible with the
Atmel
TS68K family is based on an
asynchronous data transfer.
The data exchange is mandatory on 16 bits for access to the FIFO messages (transmit-
ter) and to the message buffer (receiver). For other access it can be on byte on D0-D7
with LDS assertion or an D8-D15 with UDS assertion.
Figure 20 and Figure 21 show the read and write flow chart.
Figure 20.
Read Cycle Flow Chart
Table 11.
Description of LCU Status Register
Bit
Function
Comments
Bit 15, 13, 11
FIFO channel 3, 2, 1 empty
0: FIFO not empty
1: FIFO empty
Bit 14, 12, 10
End of transmission on channel 3, 2,
1
0: Transmission occurs
1: No transmission actually
Bit 8
RX wrong parity. This feature is
available only if self-test register bit 0
is set to 1. This bit must be reset to 0
by user when needed.
0: No wrong parity received
1: At least one receiver has received a message with wrong
parity (set by hardware).
Bit 7, 6, 5, 4, 3, 2, 1, 0
Receiving channel 8, 7, 6, 5, 4, 3, 2, 1
0: Waiting for message
1: Received correct message
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