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參數(shù)資料
| 型號(hào)： | TS68C429AVR |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT |
| 中文描述： | 3 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數(shù)： | 24/43頁 |
| 文件大?。?/td> | 1638K |
| 代理商： | TS68C429AVR |
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TS68C429A
2120A–HIREL–08/02
FIFO
The FIFO is seen as two 16-bit words. The Most Significant Word (MSW) must be writ-
ten first. The Least Significant Word (LSW) write increments the FIFO counter.
Before any write, the user should verify that the FIFO is not full. If the FIFO is full, any
write to the FIFO will be lost.
General Circuit Control
Logical Control Unit (LCU)
The LCU mainly distributes the clocks and reset within the MRT. The reset signal, active
low is an asynchronous signal. When it occurs, all registers are reset to zero except the
Label-Control-Matrix which is not initialized and the Status-Register which is set to FC00
(hex). Reset duration must be greater than 4 clk-cyc periods.
The LCU contains the Status-register. This read/write register indicates the state of the
internal operations. It is also the image of the pending interrupts if they are not masked.
Clearing a bit “RX-Channel-i” will cancel the received message and release the Mes-
sage-buffer for reception of a new message. The “End of TX on channel-i” Is set only
when the involved channel FIFO is empty. The format of the Status-Register is given
below.
Figure 19.
Status Register
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| TS68C429AVRA | 制造商:e2v Aerospace & Defense 功能描述:Multi Channel Receiver/Transmitter 84-Pin PGA 制造商:e2v technologies 功能描述:MULTI CH RCVR/TRANSMITTER 84PIN PGA - Trays |
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| TS68EN360DES01MXCL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:32-bit Quad Integrated Communication Controller |
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